MC-Sim: An efficient simulation tool for MPSoC designs

Abstract

The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip has greatly increased the design space available for system-on-chip (SoC) designers. Efficient and accurate performance estimation tools are needed to assist the designer in making design decisions. In this paper, we present MC-Sim, a heterogeneous multi-core simulator framework which is capable of accurately simulating a variety of processor, memory, NoC configurations and application specific coprocessors. We also describe a methodology to automatically generate fast, cycletrue behavioral, C-based simulators for coprocessors using a high-level synthesis tool and integrate them with MC-Sim, thus augmenting it with the capacity to simulate coprocessors. Our Cbased simulators provide on an average 45x improvement in simulation speed over that of RTL descriptions. We have used this framework to simulate a number of real-life applications such as the MPEG4 decoder and litho-simulation, and experimented with a number of design choices. Our simulator framework is able to accurately model the performance of these applications (only 7% off the actual implementation) and allows us to explore the design space rapidly and achieve interesting design implementations.

Synthesis of reconfigurable high-performance multicore systems

“…Besides the models for core processors and coprocessors, a cycleaccurate communication model is developed as well which models the communication delay for transferring data between FPGAs and core processors in the system. The details of the simulator can be found in [5]. We compared the accuracy of our generated C performance models with the corresponding RTL SystemC models generated by AutoPilot.…”

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

“…SystemC also provides support for integrating different Instruction Set Simulators (ISS) in a unified system simulation framework, as it is able to plug an independent ISS into the entire simulation framework (as a new system module), where all system modules can be activated and synchronized through a common reference clock. Furthermore, SystemC based simulators (such as [123][124][125][126][127]) can benefit from advantages of C++ language as a hardware description language while bridging the gap between hardware and software description languages [123]. In fact, one of the most important advantages of C/C++ based description languages such as SystemC (or SpecC [128], a similar alternative) is their capability to concurrently specify both hardware and software components in the design (i.e.…”

“…MPARM [123,124] is an example of such simulators. It is a full-system SystemC-based architecture simulator, enabling to model functional, performance, and power consumption aspects, as well as a complete OS for a Multi-Processor System-on-aChip (MP-SoC), in a cycle accurate manner.…”

“…Using SystemC, MPARM (or MP-ARM) can provide processor models, memory models, the AMBA bus architecture (for communication between models through ports and signals) and support for parallel programming. However, the MPARM simulator is slow and its models for processing cores are very abstract and relatively simple, lacking detailed core modeling [130].…”

Conservative application-level performance analysis through simulation of MPSoCs

“…In this section we focus on techniques that overlap with our work in some way. Multiprocessor simulation methods such as those in [5], [6] enable the production of timing results through simulation of applications running on a cycle accurately modelled platform. Simulation techniques such as these do not take into account the worst case response times of individual components by construction.…”