Measurement and Analysis of Statistical IC Operation Errors in a Memory Module Due to System-Level ESD Noise

Park, Myungjoon; Park, Junsik; Choi, Joungcheul; Kim, Jin-Woo; Jeong, Seonghoon; Seung, Manho; Lee, Seokkiu; Kim, Jingook

doi:10.1109/temc.2018.2815641

Cited by 15 publications

(4 citation statements)

References 30 publications

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“…The role of the on/off-chip decaps is vital for the reductions of the power supply coupling noises in ICs [26,27]. Such decaps are also used to prevent the oxide breakdown [28], power-ground noises [29] and conducted noises [14] due to a transient ESD event.…”

Section: Analysis Of Effect Of Decaps On Coupled Noise On Sensitive Nmentioning

confidence: 99%

“…To increase the robustness of the products against injected ESD noise, different experimental and full-wave numerical modeling techniques for system level ESD coupling analysis have been proposed in the literature. These include: failure analysis using susceptibility testing [5]; analysis of coupled ESD noise to DUT through time and frequency domain measurements [1,[10][11][12][13][14]; and full-wave EM simulation of DUT and ESD source [2,6,[15][16][17][18]. These reported techniques have limitations in terms of the requirement of the manufacturing of the DUT to perform susceptibility analysis [5], or the characterization of the coupled noise at victim positions for each different design configuration of the DUT [10][11][12][13][14]19].…”

Section: Introductionmentioning

confidence: 99%

“…In addition, the size of the injection probes used in susceptibility analysis becomes quite large compared to the small size of such ICs [6,20]. The ESD analysis using full-wave EM simulation provides more insight into the ESD noise coupling paths across multiple layers unlike [5], and thus making it more appropriate for the fast and efficient analysis of ESD coupling to DUT, compared to only experimental techniques [1,5,6,[10][11][12][13][14]. The existing studies related to ESD coupling analysis using full-wave numerical modeling, are either for a simple transmission line, circular loop and mobile phone-based DUT s [16][17][18]21] or lacks in the methodology for the systematic assessment of the sensitive traces for a realistic complete high-speed memory module.…”

Section: Introductionmentioning

confidence: 99%

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Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

et al. 2019

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This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes on the high-speed DRAM modules (DDR3 and DDR4) against injected ESD noise are determined through full-wave numerical simulations of the memory modules using the developed 3D model of the ESD gun. The validity of the full-wave numerical setup is confirmed through measurements, prior to the DOE analysis. Besides, current distribution analysis of DRAMs, seven different DOE configurations based on the number of installed decoupling capacitors (decaps) and their values on memory modules, are analyzed. The findings of DOE analysis suggests that DDR4 is less susceptible (70–80 % less) to the coupled ESD noise compared to DDR3. In addition, the command address (CA) nets are most sensitive in both memory modules. The utilization of the maximum possible number of decaps covering low, medium and high frequency ranges, as well as separate power and ground layers in memory stack-up design, increase the robustness and immunity of memory modules for the transient ESD event. The suggested approach offers time-saving and financial advantages to high-speed memory community, with the robust design of the memory products at the design stage before the start of the production phase.

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Section: Analysis Of Effect Of Decaps On Coupled Noise On Sensitive Nmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

et al. 2019

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“…Previous researchers have conducted a large amount of research on the ESD effect of IC and accumulated a lot of ESD protection circuit design and simulation experience [ 8 , 9 ]. At present, the commonly used circuit modeling schemes are the black box model based on chip port signal and the SPICE model of devices [ 10 , 11 , 12 ]. Although these models can describe the DC and AC characteristics of the circuit, it is difficult to describe the ESD effect of the device unless the model parameters are extracted by special experimental tests [ 13 ].…”

Section: Introductionmentioning

confidence: 99%

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

Chai

Liu

et al. 2023

Micromachines

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The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures. In this paper, the mixed TCAD model of the ESD protection circuit is built and simulated, and the negative transmission line pulse (TLP) injection damage experiment is carried out on the CD4069UBC chip. The circuit model consists of three-dimensional shallow trench isolation (STI) diode TCAD models and a three-dimensional multi-gate Complementary Metal-Oxide-Semiconductor (CMOS) inverter TCAD model. Moreover, the TCAD modeling is based on a 0.25 μm technology node. Through the transient simulation of the electrothermal coupling, the electrical signal of the input and output nodes of the circuit and the distribution of the electrothermal parameters in the device are obtained. Moreover, by analyzing the simulation results, the physical phenomena and the mechanisms of interference and damage mechanism during TLP injection are explained. The location and type of diode damage in the TLP injection simulation results of the circuit model are consistent with the TLP experiment damage results. The proposed ESD protection circuit model and analysis method are beneficial to ESD robustness prediction and ESD soft damage analysis of IC.

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Soft-Failures in Component-Level ESD Testing on the Example of Flip-Flop Data Retention

Schrey

2019

2019 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)

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Measurement and Analysis of Statistical IC Operation Errors in a Memory Module Due to System-Level ESD Noise

Cited by 15 publications

References 30 publications

Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

Soft-Failures in Component-Level ESD Testing on the Example of Flip-Flop Data Retention

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