Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology

Abstract

Abstract-A test-chip in a low-power 45 nm technology, featuring uniaxial strained-Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured over multiple wafers, analyzed and attributed to likely causes in the manufacturing process. Delay is characterized using an array of ring oscillators and transistor leakage current is measured with an on-chip ADC. The key results link systematic layout-dependent and die-to-die variability as being caused by gate patterning and material strain. In comparison to a previous 90 nm experiment, gate proximity now contributes less to frequency variability, causing a 2% change in overall performance, while strain has increased its contribution to about 5% of the overall performance.

Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression

“…A quadratic wafer-level pattern has been observed for a large number of physical effects, such as postexposure baking temperature related critical dimension (CD) variation [14], etch temperature related CD variation [14], and deposition rate variation of chemical vapor deposition [15]. It is shown in [4] that within-die gate CD variation can be modeled using a quadratic function, and such a pattern can be explained by the along-slit and along-scan variation of the scanner [21].…”

“…where S (l) (u, v) and R (l) (u, v) denote the DCT coefficients of the spatially correlated variation s (l) (x, y) and the uncorrelated random variation r (l) (x, y) defined in (14). Once S (l) (u, v) and R (l) (u, v) are found, s (l) (x, y) and r (l) (x, y) can be determined by IDCT.…”

“…It has been shown in (14) that for any wafer or die, the spatial variation b (l) (x, y) can be represented as the summation of the spatially correlated variation s (l) (x, y) and the random variation r (l) (x, y). We first model the spatially correlated variation using the basis functions from the physical dictionary.…”

Variability Effects in Graphene: Challenges and Opportunities for Device Engineering and Applications

“…Variability sources in the standard complementary metal-oxide-semiconductor (CMOS) process can be categorized according to their spatial characteristics, time-scales, physical/environmental origins and systematic/random components [42,43,46]. And the nature of variability is likely to change with the progress of innovative materials, fabrication methods and device structures in the targeted applications [46,[48][49][50][51][52]: some variability sources may diminish while others may emerge; some can be minimized via device engineering (e.g. variation in nominal lengths/widths) while others are limited by the material imperfection (e.g.…”

Power Variability in Contemporary DRAMs

“…Though variability measurements through simple silicon test structures abound (e.g., [8], [9]), variability characterization of full components and systems have been scarce. Moreover, such measurements have been largely limited to processors (e.g., 14X variation in sleep power of embedded microprocessors [6] and 25% performance variation in an experimental 80-core Intel processor [10]).…”