Measurement-based characterization of global memory and network contention, operating system and parallelisation overheads: case study on a shared-memory multiprocessor

Natarajan, C.; Sharma, Sanjay Kumar; Iyer, Ravishankar K.

doi:10.1109/isca.1994.288160

Cited by 4 publications

(1 citation statement)

References 14 publications

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“…System performance degrades drastically when the number of processors increases, with cache miss ratio being under 2%. With four processors in [3], the shared memory (and network) contention accounted for 1.3% to 17% of the total application execution time.…”

Section: Related Workmentioning

confidence: 99%

Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder

Kulmala

Salminen

Lehtoranta

et al.

2006 IEEE Design and Diagnostics of Electronic Circuits and Systems

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The impact of shared instruction memory on performance is measured and analyzed for an FPGAbased Multiprocessor System-on-Chip (MP-SoC) with an MPEG-4 video encoding application. Our MP-SoC architecture allows arbitrary scaling of the number of synthesized processors and includes a monitoring unit for memory transfers. Based on the measurements with up to four processors on Altera Stratix 1S40, an estimate of the effect of the shared memory for larger configurations is presented. The shared instruction memory is shown to be area-efficient and sufficient in performance for configurations up to five processors, as the drop in encoded video frame rate stays below one compared to distributed instruction memory organization.

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Section: Related Workmentioning

confidence: 99%

Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder

Kulmala

Salminen

Lehtoranta

et al.

2006 IEEE Design and Diagnostics of Electronic Circuits and Systems

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The dynamics of multitasking-multiprocessing computing

Paul

Mickle

1995

Journal of the Franklin Institute

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Characterizing the memory behavior of compiler-parallelized applications

Torrie

Martonosi

Tseng

et al. 1996

IEEE Trans. Parallel Distrib. Syst.

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Compiler-parallelized applications are increasing in importance as moderate-scale multiprocessors become common. This paper evaluates how features of advanced memory systems (e.g., longer cache lines) impact memory system behavior for applications amenable to compiler parallelization. Using full-sized input data sets and applications taken from standard benchmark suites, we measure statistics such as speedups, synchronization and load imbalance, causes of cache misses, cache line utilization, data tra c and memory costs. This exploration allows us to draw several conclusions. First, we nd that larger granularity parallelism often correlates with good memory system behavior, good overall performance, and high speedup in these applications. Second, we show that when long (512 byte) cache lines are used, many of these applications su er from false sharing and low cache line utilization. Third, we identify some of the common artifacts in compiler-parallelized codes that can lead to false sharing or other types of poor memory system performance, and we suggest methods for improving them. Overall, this study o ers both an important snapshot of the behavior of applications compiled by current parallelizing compilers, as well as an increased understanding of the interplay between cache line size, program granularity, and memory performance in moderate-scale multiprocessors.

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Measurement-based characterization of global memory and network contention, operating system and parallelisation overheads: case study on a shared-memory multiprocessor

Cited by 4 publications

References 14 publications

Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder

Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder

The dynamics of multitasking-multiprocessing computing

Characterizing the memory behavior of compiler-parallelized applications

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