Measurement of a timing error detection latch capable of sub-threshold operation

Turnquist, Matthew J.; Laulainen, Erkka; Makipaa, Jani; Pulkkinen, Mika; Koskinen, Lauri

doi:10.1109/norchp.2009.5397791

Cited by 3 publications

(4 citation statements)

References 11 publications

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“…There are two main types of EDS architectures: a dynamic node [13][14][15] and a delayed shadow latch [7,8]. Of these architectures, the dynamic node can achieve a lower power and lower clock node capacitance.…”

Section: Timing-error Detectionmentioning

confidence: 99%

“…For example, to reduce the D-ERRf delay, I TEDsc was increased from 300 pA to 1.56 nA (Figure 8). In previous designs [14,15], the uncertainty region and TED window have been fully defined at design time, which is not favorable for weak inversion TED design. Simulations showed an uncertainty region (i.e., A 2 , A 4 ) of approximately the same size as found in measurement [15].…”

Section: Tedscmentioning

confidence: 99%

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Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS

Makipaa

Turnquist

Laulainen

et al. 2012

JLPEA

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This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm 2 , and operates down to 300 mV.

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Section: Timing-error Detectionmentioning

confidence: 99%

Section: Tedscmentioning

confidence: 99%

Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS

Makipaa

Turnquist

Laulainen

et al. 2012

JLPEA

Self Cite

View full text Add to dashboard Cite

show abstract

“…One idea that exists in [49] is to re-design the Transition Detector with Time-Borrowing (TDTB) circuit [4]. By carefully sizing the transistors, they limit the V th variation and obtain the optimal drive strength ratio of NMOS to PMOS for low-V dd operation.…”

Section: Sub-threshold Timing Error Detectionmentioning

confidence: 99%

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Crop

Krimer

Moezzi-Madani

et al. 2011

JLPEA

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While Moore's law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit J. Low Power Electron. Appl. 2011, 1 335 approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well.

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“…The EDS circuit detects timing errors when transitions of data occur under a detection window. EDS circuits typically use transition detector circuits [2]- [4] or discrete samples [1]. EDS circuits are placed at each critical path in a TED (pipeline) microprocessor as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL

et al. 2011

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Timing error detection (TED) microprocessors are able to eliminate large timing margins by operating up to a voltage-frequency point in which intermittent errors occur. The detection of these errors requires an error-detection sequential (EDS) circuit. This paper presents the measurements of an EDS circuit called TEDsc. Using subthreshold source-coupled logic, TEDsc is able to dynamically adapt to system-level requirements. Measurements of TEDsc are presented in terms of a new system level TED definition. TEDsc is implemented in 65 nm CMOS, has an area of 97.5 J.lm 2 , and consumes 79 pW (Vdd=250 mY). TEDsc operates at a clock period (Tc LK) of 150 F04 at Vdd=400 m V with a sufficiently large detection window. By decreasing the size of the detection window, TEDsc can operate to at least TCLK=50 F04.

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Measurement of a timing error detection latch capable of sub-threshold operation

Cited by 3 publications

References 11 publications

Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS

Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL

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