Room temperature photoluminescence (RTPL) spectroscopy and Raman spectroscopy were examined as in-line monitoring techniques for characterizing the interface characteristics of ultra-thin (∼7.2 nm) stacked dielectric films (SiN/SiO 2 ) on 300 mm Si wafers. To investigate the effect of the stacked dielectric films on electronic properties and lattice stress of Si beneath the films, RTPL and Raman signals were measured under various excitation wavelengths with different probing depths. Changes of interface characteristics (mainly, electronic properties and lattice stress of Si beneath the films) of the stacked dielectric films and the Si wafer were investigated using various specimens prepared by different deposition techniques and conditions. The overall interface characteristics of the SiN/SiO 2 /Si specimens was found to be very dependent on the SiN deposition technique and process conditions. As the stoichiometry of SiN films change from N-rich to Si-rich conditions, the RTPL signal becomes weaker, indicating the change of electronic properties at the SiN/SiO 2 /Si interface. Within-wafer and wafer-to-wafer variations of the SiN/SiO 2 /Si interface characteristics were successfully characterized by RTPL and Raman spectroscopy under various excitation wavelengths.Other characterization results such as film thickness from ellipsometry, film stress from wafer curvature and film composition from Auger electron spectroscopy (AES) were also discussed. Advanced metal-oxide-semiconductor (MOS) and metalinsulator-semiconductor (MIS) devices employ ultra-thin dielectric film(s) as gate dielectrics. The physical dimensions are typically on the order of several nanometers. Pure SiO 2 or combinations of SiN and SiO 2 films are typically used. Both physical thickness and effective oxide thickness (EOT) are less than 10 nm.1-2 High dielectric constant materials (high-k dielectrics) and metal gates are also frequently used. Low dielectric constant materials (low-k dielectrics) are used as inter-metal dielectrics (IMD) and inter-layer dielectrics (ILD) with Cu interconnects to reduce RC constants (i.e, RC delay) and improve device operation speed.3 As devices scale to smaller size, the complexity of device structures as well as the number of interfaces in dielectric films increases. Proper understanding, monitoring and control of the dielectric/Si interface become very important.Physical dimensions of ultra-thin dielectric film(s) on Si wafers are typically measured using ellipsometry and occasionally verified by high resolution cross-section transmission electron microscopy (HRXTEM). Conventional interface characterization techniques include chemical characterization and electrical characterization. Chemical properties are typically evaluated using Auger electron spectroscopy (AES), secondary ion mass spectroscopy (SIMS) and X-ray photoelectron spectroscopy (XPS).4-6 Films stress is often monitored in blanket Si wafers by measuring the curvature, and its direction, before and after film deposition and treatment.7-10 The stoic...