Measurement of thermally induced warpage of BGA packages/substrates using phase-stepping shadow moire

Wang, Y.Y.; Hassell, Patrick

doi:10.1109/eptc.1997.723923

Cited by 33 publications

(12 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Shadow moiré and projection moiré are noncontact and nondestructive detecting methods for measuring out-of-plane displacements and can be make on-line, full-field measurements. Shadow moiré is the preferred method for larger samples, and projection moiré is more suit for smaller sample size [1]- [3]. In this paper, the simple nondestructive shadow moiré technique would be taken for discussing the warpage issues associated with the warpage deformation of silicon wafer.…”

Section: Introductionmentioning

confidence: 98%

Notice of Retraction: 3-D warpage measurement of silicon wafer

Zhang

Zhu

Song

et al. 2011

2011 2nd International Conference on Artificial Intelligence, Management Science and Electronic Commerce (AIMSEC)

View full text Add to dashboard Cite

show abstract

Section: Introductionmentioning

confidence: 98%

Notice of Retraction: 3-D warpage measurement of silicon wafer

Zhang

Zhu

Song

et al. 2011

2011 2nd International Conference on Artificial Intelligence, Management Science and Electronic Commerce (AIMSEC)

View full text Add to dashboard Cite

show abstract

“…This thermo-moire (TM) technique and equipment is common within the industry and is consistent with JEDEC specification [2,7]. The output of this warpage measurement method is a two-dimensional plot of the warpage along each package diagonal, a three-dimensional contour plot of the substrate surface, and warpage data (mean, minimum, maximum) for each package measured (see Figure 5).…”

Section: Evaluation Methodologymentioning

confidence: 98%

Controlling Top Package Warpage for POP Applications

Carson

Lee

Vijayaragavan³

2007

2007 Proceedings 57th Electronic Components and Technology Conference

View full text Add to dashboard Cite

The need to integrate devices in the vertical dimension to reduce space, thickness, and cost for handheld applications has fueled enormous growth of what can be termed 3D packaging.Due to testability, business flow, and configuration flexibility issues, the Package on Package (POP) vertical stacking solution has emerged as the preferred method to stack mobile phone logic processor with memory. The POP solution typically consists of the logic processor in the bottom package and memory device stack in the top package. The bottom package has land pads on the top perimeter in order to allow top package to be mounted and reflowed above. Both packages must be capable of being placed on the PC Board and reflowed simultaneously to each other and to the board. Control of the top and bottom package warpage is a critical issue impacting board mount yields and adoption. A series of experiments were performed to determine the impact of different materials and construction on the warpage of the top package at reflow temperature. From this work certain trends are apparent and can be used to optimize the top package warpage to assure compatibility of warpage with the bottom POP and high yields during the simultaneous reflow of the POP stack to the motherboard. POP Warpage and Board MountThe POP module consists of a bottom package, with peripheral land pads on the top surface, to allow the mounting and interconnection of a top package, which has a corresponding peripheral solder ball array (see Figure 1). Electrical interconnection of the stacked packages is achieved by means of reflow of the top package solder balls to the lands on top of the bottom package. Electrical interconnection of the bottom package is achieved by means of reflow of the bottom package to the motherboard of the product application. A typical product application for POP today is for mobile phones. The bottom package typically houses the logic base band or application processor, while the top package contains the memory devices to compliment the processor and provide the advanced features and performance required for high and mid-tier mobile phones. To allow the most configuration flexibility to the handset maker, simultaneous reflow of the top package to the bottom package on the motherboard is desired (see Figure 2). This allows the handset maker to configure and match memory size and type with processor as needed to meet the needs of a particular phone for a particular market [1]. However, simultaneous reflow of the thin top and bottom package to the motherboard, which is itself thin and typically has components mounted on both sides, can be problematic due to temperature dependent warpage of the packages, the board, and the clearances involved [1,8]. Therefore, warpage of the POP during the reflow process needs to characterized, optimized, and controlled in order to achieve acceptable board mount yields. Top Package Figure 1: POP construction cocs4#ier Ared Gc) aliability EndGaer astad liaiXLity Figure 2: schematic of simultaneous reflow Due to the const...

show abstract

“…To increase the sensitivity of the Shadow Moiré technique the Thermoiré PS88+ applies the phase stepping method, where use is being made of the grey level information contained in the fringe pattern so that the fractional fringe order may be resolved [9,10].…”

Section: Measurement Principlementioning

confidence: 99%