Measuring 6D Chip Alignment in Multi-Chip Packages

Chow, A.; Hopkins, D.; Ho, Ron; Drost, Robert

doi:10.1109/icsens.2007.4388650

Cited by 14 publications

(15 citation statements)

References 6 publications

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“…Capacitive PxC misalignment has been experimentally reported in [15]. Analytic models have also been developed for capacitive PxC misalignment and extended over to the additional cases for Optical PxC and Inductive PxC as well [16].…”

Section: Package Structure and Assemblymentioning

confidence: 98%

“…Detailed descriptions of the operating principles of the position detection circuitry can be found in [15]. A high-level overview of the electrical alignment measurements is presented here.…”

Section: Alignment Characterizationmentioning

confidence: 99%

“…For a given receiver pad size, an X, Y, and Z alignment of less than 1/3 of the pad size, or an 8 lm misalignment tolerance for 24 lm pads must be maintained [15]. Although the size of the pads could be increased to ease the alignment requirements, the bandwidth density and the power density would degrade.…”

Section: Introductionmentioning

confidence: 99%

“…Although the size of the pads could be increased to ease the alignment requirements, the bandwidth density and the power density would degrade. Therefore, to accommodate manufacturing variations of the substrate, assembly variations, and the CTE mismatch between the substrate material and silicon, the electrical steering capability is enabled to extend the misalignment tolerance in X and Y to 18 lm [12,15].…”

Section: Introductionmentioning

confidence: 99%

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Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

Sze

Popovic

Shi

et al. 2010

Microelectronics Reliability

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Section: Package Structure and Assemblymentioning

confidence: 98%

Section: Alignment Characterizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

Sze

Popovic

Shi

et al. 2010

Microelectronics Reliability

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“…The chip ( Figure 11) has a relatively large footprint of 15mm×12.5mm. The nine small rectangular structures (labeled "Z") at the center and corners of the chip are sensor structures used to measure the separation between the chip and the substrate [11]. The four large rectangular structures (labeled "P") along the four sides of the chip are used for chip-to-chip data communication [9], and are not relevant to the experiments described herein.…”

Section: The Test Ic Chipmentioning

confidence: 99%

A package demonstration with solder free compliant flexible interconnects

Shubin

Chow

Cunningham

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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Flexible, stress-engineered spring interconnects are a novel technology potentially enabling room temperature assembly approaches to building highly integrated and multi-chip modules (MCMs). Such interconnects are an essential solderfree technology facilitating the MCM package diagnostics and rework. Previously, we demonstrated the performance, functionality, and reliability of compliant micro-spring interconnects under temperature cycling, humidity bias and high-current soak. Currently, we demonstrate for the first time the package with the 1st level conventional fine pitch C4 solder bump interconnects replaced by the arrays of microsprings. Dedicated CMOS integrated circuits (ICs) have been assembled onto substrates using these integrated microsprings. Metrology modules on the ICs are designed and used to characterize the connectivity and resistance of each microspring site. IntroductionCurrent trends and progress in microelectronics continue to be enabled by chip packaging technologies. As die sizes, I/O count, and power densities grow, significant challenges develop in connecting chips to their first-level packages. Additionally, ongoing developments in 3D integration and multi-chip modules (MCMs) present new opportunities for novel I/O technologies that improve performance despite severe dimensional constraints.Electronic packaging based on stress-engineered spring interconnects [3,12] can potentially improve chip testing, rework, and mechanical compliance. With conventional flipchip bonding, the rigid solder reflown microbumps can cause package failure due to excessive shear, as there is a significant CTE mismatch between a silicon integrated circuit (IC) die and the package substrate. Spring-based interconnects, on the other hand, are flexible and compliant; they present a stressfree, lead-free packaging solution for connecting an IC die to ceramic and organic substrates. They also provide rematable connections to enable a reusable, reworkable MCM platform where an ability to separate non-functional and functional die, i.e. identifying known good die (KGD), is key to enhancing assembly yield.Previously, we have realized micro-spring prototypes that meet the stringent electrical and mechanical demands of a typical modern, high-performance microprocessor package; each spring provides <100 mΩ per connection and >30 μm of compliance; spring reliability was also confirmed under 0-100°C temperature cycling, 85/85 temperature humidity bias, and a high-current soak [1][2].

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