The local integration of III-Vs on Si is relevant for a wide range of applications in electronics and photonics, since it combines a mature and established materials platform with desired physical properties such as a direct and tunenable bandgap and high mobility. The large thermal expansion coefficient and lattice mismatch, however, pose a challenge for the direct growth of III-Vs on Si. In this paper we will review fabrication concepts to overcome this mismatch for the local integration of III-Vs on Si. In particular, we will briefly discuss processing methods based on aspect ratio trapping, nanowire growth, and template-assisted selective epitaxy. The focus of this review will be on the latter, where we will provide an overview of the different possibilities and embodiments of template-assisted selective epitaxy (TASE) and their promise for locally integrated active photonic devices.