Mechanical and microstructural characterization of high aspect ratio through-wafer electroplated copper interconnects

Abstract

In this paper we present the mechanical and microstructural characterization results of through-wafer electroplated copper interconnects. Copper was deposited in very high aspect ratio (∼15), narrow (15 µm) through-vias in silicon, which were earlier created by deep reactive ion etching. The two critical mechanical properties, i.e. hardness and modulus of elasticity, and the microstructure of the electroplated copper interconnect were determined by nanoindentation, atomic force microscope and x-ray diffraction techniques. A location-dependent hardness characteristic was shown along the length of electroplated copper interconnects. The modulus and the hardness of copper interconnects at the bottom segment (124 GPa and 1.8 GPa) were found to be higher than those at the top segment (116 GPa and 1.1 GPa). The reason behind these variable hardness values in the copper interconnect was due to the different grain sizes and the microstructure in the electroplated copper. These varying grain sizes were caused by the incremental current densities used during electrodeposition. The thermal strain, generated due to the coefficient of thermal expansion mismatch, was measured by the digital image speckle correlation technique. From the results, the thermal strain in the Y-direction was found to be more dominant than that in the X-direction. The grain sizes and the preferred texture orientation in the electroplated copper were characterized by the x-ray diffraction technique.

Fabrication of optically smooth, through-wafer silicon molds for PDMS total internal reflection-based devices

“…In the past decades, deep reactive ion etching (DRIE) has been increasingly employed in the fabrication of various MEMS devices including resonators, actuators and inertial sensors (Ishihara et al 1999;Klaassen et al 1996), micro turbines and micro engines (Mehra et al 2000;Knobloch et al 2003), micro mirrors and photonic crystals (Marxer et al 1997;Jukam and Sherwin 2003), microfluidic devices (Gray et al 1999;Richter et al 1999), and through-wafer interconnects (Nagarajan et al 2007;Dixit et al 2007), etc. The most commonly used DRIE process, namely Bosch process (Robert Bosch GmbH 1994), is composed of two alternating technical steps which are etching and passivation.…”

“…Sidewall roughness might also affect the smoothness of gear transmission where moving contact exists in micro engines devices (Mehra et al 2000;Knobloch et al 2003). In interconnects, sidewall roughness could affect the grain sizes and microstructures along the interconnect length (Dixit et al 2007). Sidewall roughness has also severely affected the performance of vibration-powered electromagnetic generator fabrication by through-wafer DRIE (Koukharenko et al 2008).…”

μ-Raman spectroscopy and FE-modeling for TSV-Stress-characterization

“…Cu [11,12] SiO 2 [13] Si [14] Deposition The presence of three normal stresses and one shear stress already disagree with the uniaxial stress thesis. FEM results clearly proof a more complicated stress distribution and a direct calculation of specific stress values out of measured Raman shifts is not possible.…”

“…For Si and SiO 2 elastic material behavior was assumed. To implement elastic-plastic properties a kinetic hardening model was assigned to Cu [12]. All material properties were modeled with a temperature dependency.…”

Manufacturing microstructured tool inserts for the production of polymeric microfluidic devices

“…Although a lower current density eliminates or reduces the size of voids, electroforming time increases significantly. Pulse reverse current electroplating has been successfully used to eliminate voids in high aspect ratio (~4.5) submicron features by dissolving the deposited metal material according to the anodic reaction [30][31][32]. The effect of current on the microstructure of a feature is shown in Figure 13.…”