Mechanical Stability Analysis via Neutral Mechanical Plane for High‐Performance Flexible Si Nanomembrane FDSOI Device

Abstract

2D properties. The crystalline structure in the 2D materials leads to improvements in device performance over the amorphous structure in organic semiconductors, but not over crystalline Si bulk substrates. [10][11][12][13] Recently, it was reported that Si bulk substrates become flexible when the thickness of the Si decreases in the nanometer range and becomes a Si nanomembrane (NM) that eventually mimics 2D materials. Using a Si NM on a polymer substrate satisfies the high-performance requirements as well as mechanical flexibility requirements. One of the key elements that enables Si NM devices being high performance is the acceptability of high-temperature processes, which are essential for source/drain dopant activation and high-quality gate dielectric growth. Unfortunately, these high-temperature processes are incompatible with the polymer substrate. Thus, a device fabrication-first and transfer-last process is a "must" for high-performance Si NM devices. [14][15][16][17][18] In this process, FETs are fabricated using a silicon-on-insulator (SOI) wafer via all the necessary high-temperature processes. [19,20] Then, the Si device layer consisting of the buried oxide, Si channel layer, SiO 2 , and polysilicon was released from the Si handling layer, and subsequently transferred onto the desired polymer substrate. Si NM flexible devices fabricated via such device fabrication-first and transfer-last process have shown excellent device performance, and their electrical results are comparable to those of Si bulk substrates. One big concern regarding Si NM flexible devices is their mechanical reliability, which is heavily associated with the location of the neutral mechanical plane (NMP). [21,22] The NMP refers to a conceptual plane within the materials or stacks where no stress is applied, either in terms of compression or tension, even under bending. In this work, a NMP optimization using both analytical and numerical modeling is conducted for Si NM FET on a polymer substrate. The NMP-optimized Si NM FET shows excellent electrical performance at an extremely low bending radius down to 1 mm without noticeable performance degradation. Figure 1a-d shows the schematic cross-sectional views of various Si-based flexible devices in recent years. The Si device layer in Figure 1a was formed on the Si handling layer, which had been grinded down to 50 µm. In case of Figure 1b-d, the Si NM device layers were released from the Si handling wafer, and then transferred onto a polymer substrate (commercially High-performance mechanically flexible Si nanomembrane (NM) fully depleted silicon-on-insulator field-effect transistors are realized via neutral mechanical plane (NMP) optimization. This NMP-optimized Si NM flexible device, using both the analytical and numerical modeling, shows excellent mechanical and electrical stability even at a bending condition with a 1 mm radius. The strain at this point is less than 0.01% that is much smaller than the strain tolerance of 0.1%. This work reveals that mechanical reliability is heavily ...

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