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2D properties. The crystalline structure in the 2D materials leads to improvements in device performance over the amorphous structure in organic semiconductors, but not over crystalline Si bulk substrates. [10][11][12][13] Recently, it was reported that Si bulk substrates become flexible when the thickness of the Si decreases in the nanometer range and becomes a Si nanomembrane (NM) that eventually mimics 2D materials. Using a Si NM on a polymer substrate satisfies the high-performance requirements as well as mechanical flexibility requirements. One of the key elements that enables Si NM devices being high performance is the acceptability of high-temperature processes, which are essential for source/drain dopant activation and high-quality gate dielectric growth. Unfortunately, these high-temperature processes are incompatible with the polymer substrate. Thus, a device fabrication-first and transfer-last process is a "must" for high-performance Si NM devices. [14][15][16][17][18] In this process, FETs are fabricated using a silicon-on-insulator (SOI) wafer via all the necessary high-temperature processes. [19,20] Then, the Si device layer consisting of the buried oxide, Si channel layer, SiO 2 , and polysilicon was released from the Si handling layer, and subsequently transferred onto the desired polymer substrate. Si NM flexible devices fabricated via such device fabrication-first and transfer-last process have shown excellent device performance, and their electrical results are comparable to those of Si bulk substrates. One big concern regarding Si NM flexible devices is their mechanical reliability, which is heavily associated with the location of the neutral mechanical plane (NMP). [21,22] The NMP refers to a conceptual plane within the materials or stacks where no stress is applied, either in terms of compression or tension, even under bending. In this work, a NMP optimization using both analytical and numerical modeling is conducted for Si NM FET on a polymer substrate. The NMP-optimized Si NM FET shows excellent electrical performance at an extremely low bending radius down to 1 mm without noticeable performance degradation. Figure 1a-d shows the schematic cross-sectional views of various Si-based flexible devices in recent years. The Si device layer in Figure 1a was formed on the Si handling layer, which had been grinded down to 50 µm. In case of Figure 1b-d, the Si NM device layers were released from the Si handling wafer, and then transferred onto a polymer substrate (commercially High-performance mechanically flexible Si nanomembrane (NM) fully depleted silicon-on-insulator field-effect transistors are realized via neutral mechanical plane (NMP) optimization. This NMP-optimized Si NM flexible device, using both the analytical and numerical modeling, shows excellent mechanical and electrical stability even at a bending condition with a 1 mm radius. The strain at this point is less than 0.01% that is much smaller than the strain tolerance of 0.1%. This work reveals that mechanical reliability is heavily ...

An ultrathin junctionless (JL) charge trap flash (CTF) thin-film transistor (TFT) with a sub-2 nm thick poly-Si channel is demonstrated for 3D stacked flash memory. It provides the excellent memory performance of faster program/erase (P/E) speed, larger memory window (>12 V), and better endurance (>10 4 cycles) than inversion-mode (IM) devices; this device also has excellent 10-year data retention at 150 °C, as well as improved on/off current ratio (>10 8 ) and subthreshold swing (SS). The transfer characteristics and the memory performance as a function of the poly-Si channel thickness (T Ch ) are also systematically investigated. Introduction: Recently, CTF TFTs constructed on poly-Si channels have attracted attention owing to their low-power performance and good 3D-integrity in 3D memory structures [1-2]. However, due to their unavoidably grainy structure, typical poly-Si based CTF TFTs face challenging issues such as low on-current (I on ), large SS, and slow P/E speed. To overcome such drawbacks, JL CTF devices that use n + -doped poly-Si channels have been proposed [2][3]. JL devices require the full depletion of the poly-Si channel to reach the off-state; therefore, the T Ch must be small. In addition, the strong demand to further increase the memory cell density is perpetually pushing the scaling down of T Ch of poly-Si.This study for the first time demonstrates JL CTF TFTs with ultrathin 2 nm thick poly-Si channels for 3D stacked flash memory. It provides excellent memory performance as well as improved switching behavior. Device Fabrication: JL CTF TFTs with ultrathin poly-Si channels can be easily applied to vertical NAND applications ( Fig. 1(a)). To show the electrical properties of these JL CTF devices, simple planar TFTs were prepared ( Fig. 1(b)). Figs. 1(b)-(f) show the schematic, TEM images, and fabrication process. As a channel layer, 10 nm thick amorphous-Si was deposited and crystallized. Then, the thickness of the crystallized poly-Si layer was reduced by thermal oxidation and oxide removal using a dilute HF solution ( Fig. 1(g)). Thermal oxides (6 nm) / Si 3 N 4 (7 nm) / Al 2 O 3 (15 nm) were used for the gate stack. The channel doping concentration was ~10 19 cm -3 , measured using SIMS. TEM imagery confirms that a 2 nm thickness of thin poly-Si channel is uniformly formed. Results and Discussion: The JL device with the 2 nm channel shows an on/off current ratio larger than 10 8 ; a dramatic increase of the on-current is achieved compared to that of IM devices (Fig. 2). Although the SS of the JL device is larger than that of the IM device when comparing 7 nm thick devices, the SS is significantly improved as the T Ch is reduced and can be further improved when a 3D gate structure is used. Meanwhile, it is interesting that the 2 nm JL device shows an I on higher than that of the 7 nm JL device. Moreover, this can be more clearly observed in IM devices (Fig. 3). These phenomena can be understood by considering the improved interface quality that results from repetitive thermal oxidation. In ...

We investigated the dependence of grain size on the performance of a polycrystalline silicon (poly-Si) channel TFT for application to 3D NAND Flash memory devices. It has been found that the device performance and memory characteristics are strongly affected by the grain size of the poly-Si channel. Higher on-state current, faster program speed, and poor endurance/reliability properties are observed when the poly-Si grain size is large. These are mainly attributed to the different local electric field induced by an oxide valley at the interface between the poly-Si channel and the gate oxide. In addition, the trap density at the gate oxide interface was successfully measured using a charge pumping method by the separation between the gate oxide interface traps and traps at the grain boundaries in the poly-Si channel. The poly-Si channel with larger grain size has lower interface trap density.

Extremely thin silicon show good mechanical flexibility because of their 2-D like structure and enhanced performance by the quantum confinement effect. In this paper, we demonstrate a junctionless FET which reveals a room temperature quantum confinement effect (RTQCE) achieved by a valley-engineering of the silicon. The strain-induced band splitting and a quantum confinement effect induced from ultra-thin-body silicon are the two main mechanisms for valley engineering. These were obtained from the extremely well-controlled silicon surface roughness and high tensile strain in silicon, thereupon demonstrating a device mobility increase of ~500% in a 2.5 nm thick silicon channel device.