Dependence of Grain Size on the Performance of a Polysilicon Channel TFT for 3D NAND Flash Memory

Kim, Seung-Yoon; Park, Jong Kyung; Hwang, Wan Sik; Lee, Seungjun; Lee, Ki-Hong; Pyi, Seung-Ho; Cho, Byung Jin

doi:10.1166/jnn.2016.12251

Cited by 15 publications

(5 citation statements)

References 2 publications

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“…RTN improves for larger cells and smaller average grain size, as shown in Figure 40 [326,334] (where it was measured above the threshold). Other works also reported poor reliability and higher variability in 3D NAND for large poly-Si grain size [317,335]. This is because the larger number of grains associated with their smaller size results in a self-averaging effect, as discussed in [336] for the case of a polysilicon gate in a planar transistor.…”

Section: Polysilicon Grainsmentioning

confidence: 98%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: Polysilicon Grainsmentioning

confidence: 98%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…The basic concepts were developed with metals, where processing by hot and cold forming in combination with annealing is determinant in tuning their mechanical properties [39,40]. With a transfer of these concepts to classical semiconductors (Si, Ge), the attention focussed on the morphology dependence of the electrical properties [4,6,10,11], where advances of microelectronics draw the interest on grain growth in thin layers on a substrate, with semiconductors and metals as well [16,28,41,42]. Recently, grain growth with emerging organic or hybrid compounds has set a new focus on e.g.…”

Section: Fundamentalsmentioning

confidence: 99%

“…As the defects associated with grain boundaries may induce losses, their volumetric fraction should be low compared to that of the ordered grains. As a consequence, the grain size is a crucial parameter, not only with conventional semiconductors like Si [9][10][11], but also with a number of currently emerging materials, such as halide perovskites [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

Relevance of processing parameters for grain growth of metal halide perovskites with nanoimprint

et al. 2021

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The quality and the stability of devices prepared from polycrystalline layers of organic–inorganic perovskites highly depend on the grain sizes prevailing. Tuning of the grain size is either done during layer preparation or in a post-processing step. Our investigation refers to thermal imprint as the post-processing step to induce grain growth in perovskite layers, offering the additional benefit of providing a flat surface for multi-layer devices. The material studied is MAPbBr3; we investigate grain growth at a pressure of 100 bar and temperatures of up to 150 °C, a temperature range where the pressurized stamp is beneficial to avoid thermal degradation. Grain coarsening develops in a self-similar way, featuring a log-normal grain size distribution; categories like ‘normal’ or ‘secondary’ growth are less applicable as the layers feature a preferential orientation already before imprint-induced grain growth. The experiments are simulated with a capillary-based growth law; the respective parameters are determined experimentally, with an activation energy of Q ≈ 0.3 eV. It turns out that with imprint as well the main parameter relevant to grain growth is temperature; to induce grain growth in MAPbBr3 within a reasonable processing time a temperature of 120 °C and beyond is advised. An analysis of the mechanical situation during imprint indicates a dominance of thermal stress. The minimization of elastic energy and surface energy together favours the development of grains with (100)-orientation in MaPbBr3 layers. Furthermore, the experiments indicate that the purity of the materials used for layer preparation is a major factor to achieve large grains; however, a diligent and always similar preparation of the layer is equally important as it defines the pureness of the resulting perovskite layer, intimately connected with its capability to grow. The results are not only of interest to assess the potential of a layer with respect to grain growth when specific temperatures and times are chosen; they also help to rate the long-term stability of a layer under temperature loading, e.g. during the operation of a device.

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“…It is clear that GB traps are much more effective in modulating the electron conduction and result in larger V T fluctuations. In spite of these encouraging results, several important features of this model still have to be assessed, such as the actual grain size [103][104][105], the mobility degradation and conduction process at the grain boundaries [106,107], and the impact of all these quantities, including architectural parameters and cell design, on RTN.…”

Section: Polysilicon Conductionmentioning

confidence: 99%

Random Telegraph Noise in 3D NAND Flash Memories

et al. 2021

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In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of the string silicon channels on current transport. Starting from that, experimental data for RTN in 3D arrays are presented and explained via theoretical and simulation models. The attention is drawn, in particular, to the changes in the RTN dependences on the array working conditions that resulted from the transition from planar to 3D architectures. Such changes are explained by considering the impact of highly-defective grain boundaries on percolative current transport in cell channels in combination with the localized nature of the RTN traps.

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Dependence of Grain Size on the Performance of a Polysilicon Channel TFT for 3D NAND Flash Memory

Cited by 15 publications

References 2 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Relevance of processing parameters for grain growth of metal halide perovskites with nanoimprint

Random Telegraph Noise in 3D NAND Flash Memories

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