Mechanically induced strain enhancement of metal–oxide–semiconductor field effect transistors

Haugerud, B.M.; Bosworth, Lucy A.; Belford, R. E.

doi:10.1063/1.1602562

Cited by 64 publications

(32 citation statements)

References 17 publications

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“…In a second step, we determine the impact of CDU and overlay on the stress layers. Compressive or tensile stress layers are used with both planar and FinFET devices to induce strain in the channel region [5]. These layers are deposited on top of the spacers, and consist of either a single material or complex multilayers.…”

Section: Fig7mentioning

confidence: 99%

Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node

et al. 2007

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In this paper the impact of overlay and CD uniformity specifications on device and SRAM cell functional and parametric yield are analyzed. The variation of channel strain due to partial etching of the stress layer is determined, and we find that including this effect in the device parametric yield leads to severe CDU and overlay requirements. The method is applied to SRAM cells and memories, and it is shown that only the co-optimization of SRAM cell layout, CDU and overlay can increase the number of good dies per wafer.

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Section: Fig7mentioning

confidence: 99%

Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node

et al. 2007

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“…For instance, mobility values as high as 1300 cm 2 /Vs have been measured in p-type transistors fabricated from individual Si NWs [5]. Residual strain in the NW (leading to a reduction of the effective mass) probably accounts for this spectacular mobility increase compared to bulk Si [6] although more studies are needed to completely clarify this effect. Since Si NWs can be grown and doped at low temperature ($4501C and below depending on the metal catalyst) using the vapour-liquid-solid (VLS) process [7], there is no need for refractory substrates.…”

Section: Introductionmentioning

confidence: 97%

Nanowire-based active matrix backplanes for the control of large area X-ray imagers

Pribat

Cojocaru

2006

Nuclear Instruments and Methods in Physics Research Section A:

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International audienceIn digital X-ray sensors, pixel complexity is limited by the instabilities of amorphous silicon transistors or by the lack of homogeneity of their polycrystalline silicon counterparts. Here, we present a novel approach to the fabrication of thin-film transistors, based on the use of silicon nanowires grown in porous alumina templates. Transistors made from silicon nanowires are essentially studied for the post-MOS era and they exhibit excellent transport characteristics. The technology we propose is simple, as it only employs chemical vapour deposition processes for transistor fabrication. Also, as far as active matrix fabrication is concerned, a small number of masks is needed and we present a 5 mask process for the fabrication of an X-ray panel with pixel amplification

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“…High channel mobility and isolation can be obtained with a strained silicon layer on top of an insulator or a quartz substrate. The work presented here is part of a larger research program of elevated-temperature hetero-bonding to produce low level strained silicon (Belford 2001;Haugerud et al 2003Haugerud et al , 2004 on quartz (SSOQ) (Belford 2002(Belford , 2003 . The initial thrust of our effort is to bond silicon to quartz at elevated temperatures.…”

Section: Introductionmentioning

confidence: 99%

Surface activation using remote plasma for silicon to quartz wafer bonding

Belford

Sood

2008

Microsyst Technol

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A pre-wafer-bonding remote-plasma treatment is presented as a route to hydrophilic elevated temperature wafer bonding. This particular remote plasma technique was used as a non-etching surface activation technique. We report a post anneal surface energy of 2,250 mJ/m 2 using remote plasma activation which is higher than other reported results. Furthermore, the trend in increasing surface energy with increased with plasma exposure time showed no tail-off. The surface damage present in other plasma techniques is avoided and as a consequence exposure times could be extended. An increase in pre-bonding remote plasma treatment times resulted in increased surface energy, this held true for; initial pre-anneal bonding where van der Waals forces hold the wafers together, for ambient covalent bonding, and, for elevated temperature covalent bonding. It also held true for homo and heterowafer bonding. Increased surface energy was evident over a variety of bonding and annealing conditions. Surface energies or more descriptively, bonding energies result are reported for Si to Si and Si to quartz bonding and compared with various other pre-bonding treatments. Attention is focused on results obtained by varying different plasma parameters; exposure time, gas species, etc., and their effect on the surface energy of bonded pair. For silicon to quartz, we report an annealing temperature of 200°C without de-bonding, which is an extension of 50°C over previously reported values. Pre-and post plasma surface roughness measurements were made using an atomic force microscope while bond interface was characterized using scanning acoustic microscopy.

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Mechanically induced strain enhancement of metal–oxide–semiconductor field effect transistors

Cited by 64 publications

References 17 publications

Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node

Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node

Nanowire-based active matrix backplanes for the control of large area X-ray imagers

Surface activation using remote plasma for silicon to quartz wafer bonding

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