Meeting overlay requirements for future technology nodes with in-die overlay metrology

Abstract

As a consequence of the shrinking sizes of the integrated circuit structures, the overlay budget shrinks as well. Overlay is traditionally measured with relatively large test structures which are located in the scribe line of the exposure field, in the four corners. Although the performance of the overlay metrology tools has improved significantly over time it is questionable if this traditional method of overlay control will be sufficient for future technology nodes. For advanced lithography techniques like double exposure or double patterning, in-die overlay is critical and it is important to know how much of the total overlay budget is consumed by in-die components.We reported earlier that small overlay targets were included directly inside die areas and good performance was achieved 1 . This new methodology enables a wide range of investigations. This provides insight into processes which were less important in the past or not accessible for metrology. The present work provides actual data from productive designs, instead of estimates, illustrating the differences between the scribe line and in-die registration and overlay. The influence of the pellicle on pattern placement on mask and wafer overlay is studied. Furthermore the registration overlay error of the reticles is correlated to wafer overlay residuals. The influence of scanner-induced distortions (tool to tool differences) on in-die overlay is shown. Finally, the individual contributors to in-die-overlay are discussed in the context of other overlay contributors. It is proposed to use in-die overlay and registration results to derive guidelines for future overlay and registration specifications. It will be shown that new overlay correction schemes which take advantage of the additional in-die overlay information need to be considered for production.

Metrology in times of shrinking budgets

“…In the 2000s the emphasis shifted to using the tools to characterize and monitor semiconductor lithography processes and how to control them better. References [1][2][3][4][5][6][7][8][9][10][11] are the top downloaded papers from the Proceedings of SPIE in this Conference for the past 25 years, as supplied by the Director of Publications of SPIE [23]. The top paper [1] had more than 350 downloads as of the writing of this paper.…”

“…References [1][2][3][4][5][6][7][8][9][10][11] are the top downloaded papers from the Proceedings of SPIE in this Conference for the past 25 years, as supplied by the Director of Publications of SPIE [23]. The top paper [1] had more than 350 downloads as of the writing of this paper. Reading through these papers one can see 6 of 11 deal with scanner overlay, 2 deal with measurement of CDU from lithography, 1 deals with focus measurement of the scanner, 1 deals with optimizing the structure of the wafer target to measure scanner dose and overlay, and 1 with the forbidden pitch problem of optical proximity correction.…”

Atomic Scale Overlay Control

“…For each target design and axis the average OMF (Figure 4(a)) is reasonably consistent from wafer to wafer. Based on the site-to-site variation (Figure 4 at the reticle (7) and are therefore the same in every field and wafer. The site to site OMF variability in Figure 4(b) cannot arise at the reticle.…”