In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1).This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm 2 , providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results.Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.

We report on two ddfferent technologies for deformable micromirror devices as phase modulating light valves for high resolution optical applications. Both technologies are compatible with a 30V CMOS technology for active matrix addressing. We have developed and fabricated a 512 x 464 pixel light valve with CMOS addressing and viscoelastic layer deformable mirrors on top. The performance of the light valve has been Idemonstrated by an application for fast submicron laser direct writing. Furthermore we report on promosing results on cantilever-type deformable mirrors to be integrated with the CMOS active matrix.

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