Memory access dependencies in shared-memory multiprocessors

Dubois, Michel; Scheurich, C.

doi:10.1109/32.55094

Cited by 79 publications

(34 citation statements)

References 23 publications

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“…Some of them [2,29] also relax the store atomicity [5,14] constraint. A write may not be available to all processors at once: it could be at first initiated by a given processor, then committed to a store buffer or a cache, and finally globally performed to memory [22], at which point only it will be available for all processors to see. Hence the value of a given write may be available to certain processors sooner than to others.…”

Section: Weak Memory Modelsmentioning

confidence: 99%

“…6). This order corresponds roughly to the vendor documentation concept of memory events being globally performed [2,22]: a write in ghb represents the point in global time when this write becomes visible to all processors; whereas a read in ghb represents the point in global time when the read takes place. We will formalise this notion later on, at Sect.…”

Section: Global Happens-beforementioning

confidence: 99%

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A formal hierarchy of weak memory models

Alglave

2012

Form Methods Syst Des

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We present in this paper a formal generic framework, implemented in the Coq proof assistant, for defining and reasoning about weak memory models. We first present the three axioms of our framework, with several examples as illustration and justification. Then we show how to implement several existing weak memory models in our framework, and prove formally that our implementation is equivalent to the native definition for each of these models.

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Section: Weak Memory Modelsmentioning

confidence: 99%

Section: Global Happens-beforementioning

confidence: 99%

A formal hierarchy of weak memory models

Alglave

2012

Form Methods Syst Des

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“…Under a weakly ordered 7 model, invalidations do not cause access penalties as long as the processors await pending invalidations at synchronization points.…”

Section: Release Consistencymentioning

confidence: 99%

Boosting the performance of shared memory multiprocessors

Stenström

Brorsson²,

Dahlgren³

et al. 1997

Computer

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“…2.3). This order corresponds roughly to the vendor documentation concept of memory events being globally performed [21,13]: a write in ghb → represents the point in global time when this write becomes visible to all processors; whereas a read in ghb → represents the point in global time when the read takes place. There remain key choices as to which relations we include in ghb → (i.e.…”

Section: Global Happens-beforementioning

confidence: 99%

Fences in Weak Memory Models

Alglave

Maranget

Sarkar

et al. 2010

Computer Aided Verification

122

158

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Abstract. We present a class of relaxed memory models, defined in Coq, parameterised by the chosen permitted local reorderings of reads and writes, and the visibility of inter-and intra-processor communications through memory (e.g. store atomicity relaxation). We prove results on the required behaviour and placement of memory fences to restore a given model (such as Sequential Consistency) from a weaker one. Based on this class of models we develop a tool, diy, that systematically and automatically generates and runs litmus tests to determine properties of processor implementations. We detail the results of our experiments on Power and the model we base on them. This work identified a rare implementation error in Power 5 memory barriers (for which IBM is providing a workaround); our results also suggest that Power 6 does not suffer from this problem.

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Memory access dependencies in shared-memory multiprocessors

Cited by 79 publications

References 23 publications

A formal hierarchy of weak memory models

A formal hierarchy of weak memory models

Boosting the performance of shared memory multiprocessors

Fences in Weak Memory Models

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