Memory bandwidth optimizations for wide-bus machines

Alexander, Michael; Bailey, M. W.; Childers, Bruce R.; Davidson, Jack W.; Jinturkar, Sanjay

doi:10.1109/hicss.1993.270618

Cited by 10 publications

(12 citation statements)

References 10 publications

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“…Previous algorithms [1,6,27,31] cannot optimize either example. Figure 3(a) is an example in which two 32-bit integer loads are combined.…”

Section: Figurementioning

confidence: 95%

“…As a result, we can get equal or better performance 1 along the left-hand path of Figure 3(a) than the previous algorithms. Since most of the programs 1 The sign-extension instruction (sxt4) can be eliminated when we use the sign-extension elimination algorithm [21]. If both sign extensions can be eliminated, the performance of our approach will be equivalent to that of the previous approach.…”

Section: Figurementioning

confidence: 97%

“…(2) We sort candidates based on the total execution frequency computed by (1) and limit the number of candidates to reduce the compilation time.…”

Section: Our Algorithmmentioning

confidence: 99%

“…Compute combinable instruction sets (1) Compute five sets for the input of dataflow analysis (2) Solve dataflow equations using the sets computed by step (2) (3)…”

Section: Our Algorithmmentioning

confidence: 99%

“…Previous approaches for memory access coalescing focus only on array access instructions related to loop induction variables [1,6,27,31], and thus they miss many other opportunities.…”

Section: Introductionmentioning

confidence: 99%

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Instruction combining for coalescing memory accesses using global code motion

Kawahito

Komatsu

Nakatani

2004

Proceedings of the 2004 Workshop on Memory System Performance - MSP '04

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Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it for coalescing memory accesses, we can reduce the memory traffic by combining narrow memory references with contiguous addresses into a wider reference for taking advantage of a wide-bus architecture. Coalescing memory accesses can improve performance for two reasons: one by reducing the additional cycles required for moving data from caches to registers and the other by reducing the stall cycles caused by multiple outstanding memory access requests. Previous approaches for memory access coalescing focus only on array access instructions related to loop induction variables, and thus they miss many other opportunities. In this paper, we propose a new algorithm for instruction combining by applying global code motion to wider regions of the given program in search of more potential candidates. We implemented two optimizations for coalescing memory accesses, one combining two 32-bit integer loads and the other combining two single-precision floating-point loads, using our algorithm in the IBM Java™ JIT compiler for IA-64, and evaluated them by measuring the SPECjvm98 benchmark suite. In our experiment, we can improve the maximum performance by 5.5% with little additional compilation time overhead. Moreover, when we replace every declaration of double for an instance variable with float, we can improve the performance by 7.3% for the MolDyn benchmark in the JavaGrande benchmark suite. Our approach can be applied to a variety of architectures and to programming languages besides Java.

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“…Previous algorithms [1,6,27,31] cannot optimize either example. Figure 3(a) is an example in which two 32-bit integer loads are combined.…”

Section: Figurementioning

confidence: 95%

Section: Figurementioning

confidence: 97%

“…(2) We sort candidates based on the total execution frequency computed by (1) and limit the number of candidates to reduce the compilation time.…”

Section: Our Algorithmmentioning

confidence: 99%

“…Compute combinable instruction sets (1) Compute five sets for the input of dataflow analysis (2) Solve dataflow equations using the sets computed by step (2) (3)…”

Section: Our Algorithmmentioning

confidence: 99%

“…Previous approaches for memory access coalescing focus only on array access instructions related to loop induction variables [1,6,27,31], and thus they miss many other opportunities.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Instruction combining for coalescing memory accesses using global code motion

Kawahito

Komatsu

Nakatani

2004

Proceedings of the 2004 Workshop on Memory System Performance - MSP '04

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Aggressive loop unrolling in a retargetable, optimizing compiler

Davidson

Jinturkar

1996

Lecture Notes in Computer Science

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A well-known code transformation for improving the run-time performance of a program is loop unrolling. The most obvious benefit of unrolling a loop is that the transformed loop usually requires fewer instruction executions than the original loop. The reduction in instruction executions comes from two sources: the number of branch instructions executed is reduced, and the control variable is modified fewer times. In addition, for architectures with features designed to exploit instruction-level parallelism, loop unrolling can expose greater levels of instructionlevel parallelism. Loop unrolling is an effective code transformation often improving the execution performance of programs that spend much of their execution time in loops by 10 to 30 percent. Possibly because of the effectiveness of a simple application of loop unrolling, it has not been studied as extensively as other code improvements such as register allocation or common subexpression elimination. The result is that many compilers employ simplistic loop unrolling algorithms that miss many opportunities for improving run-time performance. This paper describes how aggressive loop unrolling is done in a retargetable optimizing compiler. Using a set of 32 benchmark programs, the effectiveness of this more aggressive approach to loop unrolling is evaluated. The results show that aggressive loop unrolling can yield additional performance increase of lO to 20 percent over the simple, naive approaches employed by many production compilers.

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Sarkar

2001

International Journal of Parallel Programming

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Memory bandwidth optimizations for wide-bus machines

Cited by 10 publications

References 10 publications

Instruction combining for coalescing memory accesses using global code motion

Instruction combining for coalescing memory accesses using global code motion

Aggressive loop unrolling in a retargetable, optimizing compiler

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