Memory controller policies for DRAM power management

Abstract

The increasing importance of energy e ciency has produced a m ultitude of hardware devices with various power management features. This paper investigates memory controller policies for manipulating DRAM power states in cache-based systems. We develop an analytic model that approximates the idle time of DRAM chips using an exponential distribution, and validate our model against trace-driven simulations. Our results show that, for our benchmarks, the simple policy of immediately transitioning a DRAM chip to a lower power state when it becomes idle is superior to more sophisticated policies that try to predict DRAM chip idle time.

Delay-Hiding energy management mechanisms for DRAM

“…Energy consumption can be reduced by putting the rank into a low-power state during the idle period between two consecutive I/Os. To avoid powering down rank that will be immediately accessed, power management techniques for VM use a timeout scheme that usually waits for a few nanoseconds for more memory I/Os to arrive before powering down the rank [5]. The access granularity for file I/O is coarser: the idle period between two consecutive memory I/Os in buffer cache is on the order of hundreds of microseconds.…”

A Gray-Box Feedback Control Approach for System-Level Peak Power Management

“…A lot of existing working focused on how to reduce power consumption by improving the energy-efficiency of individual server components, from processors [25] [21], to memory [14][32] and disk [46]. To address power management on system-level, Lu et al [29] presented a power reduction technique at OS-level using task-based power management.…”

A comprehensive approach to DRAM power management

“…They demonstrate good results for cacheless systems using Rambus DRAM. Fan et al [11] extend this work for systems with multi-level caches, and Irani et al [19] give a theoretical analysis of dynamic power management in memory controllers. These approaches are difficult to tune because they use thresholds, which are system and application dependent.…”