Memory controllers for high-performance and real-time MPSoCs

Åkesson, Benny; Huang, Po‐Chun; Clermidy, Fabien; Dutoit, Denis; Goossens, Kees; Chang, Yuan-Hao; Kuo, Tei-Wei; Vivet, Pascal; Wingard, Drew

doi:10.1145/2039370.2039374

Cited by 18 publications

(19 citation statements)

References 34 publications

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“…For such controllers, it is important to bound the memory efficiency, which is the fraction of clock cycles with useful data on the data bus. To guarantee high efficiency bounds, these controllers typically employ a close-page policy, which means that they close the open row immediately after every memory access to reduce the worstcase overhead of opening another row [1].…”

Section: B Real-time Memory Controllersmentioning

confidence: 99%

“…To reduce cost, main memory is shared between applications. This makes it challenging to verify that real-time requirements are satisfied unless the memory controller provides guarantees on worstcase performance [1]. Mobile platforms furthermore have strict power budgets [2] and reducing memory power consumption is identified as an important challenge to satisfy the power constraints of future mobile devices [3].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

DRAM selection and configuration for real-time mobile systems

Gomony¹,

Weis²,

Åkesson³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-The performance and power consumption of mobile DRAMs (LPDDRs) depend on the configuration of system-level parameters, such as operating frequency, interface width, request size, and memory map. In mobile systems running both realtime and non-real-time applications, the memory configuration must satisfy bandwidth requirements of real-time applications, meet the power consumption budget, and offer the best averagecase execution time to the non-real-time applications. There is currently no well-defined methodology for selecting a suitable memory configuration for real-time mobile systems. The worstcase bandwidth, average-case execution time, and power consumption of mobile DRAMs across generations have furthermore not been investigated. This paper has two main contributions. 1) We analyze the worst-case bandwidth, average-case execution time, and power consumption of mobile DRAMs across three generations: LPDDR, LPDDR2 and Wide-IO-based 3D-stacked DRAM. 2) Based on our analysis, we propose a methodology for selecting memory configurations in real-time mobile systems. We show that LPDDR (32-bit IO), LPDDR2 (32-bit IO) and 3D-DRAM (128-bit IO) provide worst-case bandwidth up to 0.75 GB/s, 1.6 GB/s and 3.1 GB/s, respectively. We furthermore show for an H.263 decoder that LPDDR2 and 3D-DRAM reduce power consumption with up to 25% and 67%, respectively, compared to LPDDR, and reduce the execution time with up to 18% and 25%.

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Section: B Real-time Memory Controllersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

DRAM selection and configuration for real-time mobile systems

Gomony¹,

Weis²,

Åkesson³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

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“…It should provide bounds on the time to perform individual load/store operations. Such memory controllers are described for instance in [30], [31].…”

Section: Execution Platformsmentioning

confidence: 99%

Predictable dynamic embedded data processing

Geilen

Stuijk

Basten³

2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-Cyber-physical systems interact with their physical environment. In this interaction, non-functional aspects, most notably timing, are essential to correct operation. In modern systems, dynamism is introduced in many different ways. The additional complexity threatens timely development and reliable operation. Applications often have different modes of operation with different resource requirements and different levels of required quality-of-service. Moreover, multiple applications in dynamically changing combinations share a platform and its resources. To preserve efficient development of such systems, dynamism needs to be taken into account as a primary concern, not as a verification or tuning effort after the design is done. This requires a model-driven design approach in which timing of interaction with the physical environment is taken into consideration; formal models capture applications and their platforms in the physical environment. Moreover, platforms with resources and resource arbitration are needed that allow for predictable and reliable behavior to be realized. Run-time management is further required to deal with dynamic use-cases and dynamic trade-offs encountered at run-time. In this paper, we present a model-driven approach that combines model-based design and synthesis with development of platforms that support predictable, repeatable, composable realizations and a run-time management approach to deal with dynamic use-cases at run-time. A formal, compositional model is used to exploit Pareto-optimal trade-offs in the system use. The approach is illustrated with dataflow models with dynamic application scenarios, a predictable platform architecture and run-time resource management that determines optimal trade-offs through an efficient knapsack heuristic.

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“…Others have investigated system architectures using 3D-integrated on-chip DRAM [17], [18], [19], [20]. In [3], Weis et al present a design space exploration of SoCs with 3D-stacked DRAM and in [21] the authors show an overview of 3D-integrated DRAMs and the challenges associated with it. In this work we assume a specific 3D-stacked DRAM architecture, i.e.…”

Section: Related Workmentioning

confidence: 99%

A distributed interleaving scheme for efficient access to WideIO DRAM memory

Seiculescu

Benini

Micheli

2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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Achieving the main memory (DRAM) required bandwidth at acceptable power levels for current and future applications is a major challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM memories promise to provide a significant boost in bandwidth at low power levels by exploiting multiple channels and wide data interfaces. In this paper, we address the problem of efficiently exploiting the multiple channels provided by standard (JEDEC's WIDE-IO) 3D-stacked memories, to extract maximal effective bandwidth and minimize latency for main memory access. We propose a new distributed interleaved access method that leverages the on-chip interconnect to simplify the design and implementation of the DRAM controller, without impacting performance compared to traditional centralized implementations. We perform experiments on realistic workload for a mobile communication and multimedia platform and show that our proposed distributed interleaving memory access method improves the overall throughput while minimally impacting the performance of latency sensitive communication flows.

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Memory controllers for high-performance and real-time MPSoCs

Cited by 18 publications

References 34 publications

DRAM selection and configuration for real-time mobile systems

DRAM selection and configuration for real-time mobile systems

Predictable dynamic embedded data processing

A distributed interleaving scheme for efficient access to WideIO DRAM memory

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