Memory Effect of Metal—Insulator—Silicon Capacitors with SiO ₂ /HfO ₂ /Al ₂ O ₃ Dielectrics

Abstract

Charge trapping characteristics of the metal-insulator-silicon (MIS) capacitors with SiO2/HfO2/Al2O3 stacked dielectrics are investigated for memory applications. A capacitance-voltage hysteresis memory window as large as 7.3 V is achieved for the gate voltage sweeping of ±12 V, and a flat-band voltage shift of 1.5 V is observed in terms of programming under 5 V and 1 ms. Furthermore, the time-and voltage-dependent charge trapping characteristics are also demonstrated, the former is related to charge trapping saturation and the latter is ascribed to variable tunnelling barriers for electron injecting and discharging under different voltages.

The Effect of Thermal Treatment Induced Performance Improvement for Charge Trapping Memory with Al2O3/(HfO2)0.9(Al2O3)0.1/Al2O3 Multilayer Structure

“…Besides, S2 shows earlier program saturation than S1, indicates that the electron trapping occurs dominantly at the initial stage of programming, followed by slower charge trapping. 29 From Fig. 6, we also noticed that the erasing speed for S2 (| V FB | reaches 4.84 V after erasing at −10 V for 100 ms) is slightly higher than that for S1 (| V FB | is 3.97 V after erasing at −10 V for 100 ms).…”