Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation

Sung, Tze-Yun; Sun, Mao-Jen; Shieh, Yaw-Shih; Hsin, Hsi-Chin

doi:10.1007/11949534_80

“…Sung [17] proposed a CORDIC-based FDCT/IDCT architecture, composed by two 1-D units, an SRAM for transposition and a coefficients ROM. Our architecture is 18 times more energy efficient than [17].…”

Section: Synthesis Resultsmentioning

confidence: 99%

An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms

Livramento

¹

,

Moraes

²

,

Machado

³

et al. 2011

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design

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The development of mobile multimedia devices follows the platform-based design methodology in which IP cores are the building blocks. In the context of mobile devices there is a concern of battery lifetime which leads to the need of energyefficient IP cores. This paper presents an energy-efficient FDCT/IDCT configurable IP core. Synthesis for 90 nm resulted in 50 MHz as maximum frequency and 1.66 mW as total power, achieving a throughput of 188.2 Mpixels/s, which is enough to process two HDTV@1080p videos in real time. The IP core architecture is based on Massimino's algorithm, which was chosen for its accuracy and parallelism. The exploration of its parallelism resulted in a fully-combinational 1-D FDCT/IDCT configurable datapath. In addition, the IP core is IEEE-1180 compliant. Comparisons with related work, in terms of energy efficiency (mJ/Mpixel), revealed that our architecture is at least 64% more efficient than other DCT architectures.

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“…The proposed fast 2-D DCT / IDCT processor Based on the proposed algorithm, the architecture of 2-D DCT(IDCT) can be implemented with two successive 1-D DCT(IDCT) processors and only one transpose memory [1][2][3]. The proposed architecture of 2-D DCT and IDCT is shown in Fig.…”

Section: Cmentioning

confidence: 99%

“…The conventional DCT architectures using distributed arithmetic involve complex hardware with high computation complexity [1][2][3][4][5][6][7][8][9][10]. The fast DCT architectures with low computation complexity are based on Loeffler proposed architecture using Flow-Graph Algorithm (FGA) [11][12][13].…”

mentioning

confidence: 99%

A novel VLSI linear array for 2-D DCT/IDCT

Huang

¹

,

Sung

²

,

Shieh

³

2010

2010 3rd International Congress on Image and Signal Processing

Self Cite

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This paper proposes an efficient one-dimensional (1-D) N-point discrete cosine and inverse discrete cosine transform (DCT/IDCT) architectures using sub-band decomposition algorithm. Based on the row-column decomposition technique, the two-dimensional (2-D) N×N DCT/IDCT architecture with two successive 1-D DCT/IDCT processors and one transpose memory is proposed. The orthonormal property of DCT/IDCT transformation matrices is fully used to simplify the hardware complexities. The proposed architectures with computation complexity O(5N/8) and O(3N/8) for DCT and IDCT, respectively, and low hardware complexity O(3N/8) for both DCT and IDCT are fully pipelined and scalable for variable-length 2-D DCT/IDCT computation.

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“…The 3-D AIQ proposed by Wahid is sparser than Fu's 2-D AIQ and thus, requires fewer adders. Sung [21] uses two 1-D DCT blocks with an SRAM transpose buffer. Sung also reduces power consumption by implementing multipliers with Double-Rotation CORDIC algorithm in a circular coordinate system.…”

Section: Review Of Related Workmentioning

confidence: 99%

“…A Ar rc ch hi it te ec ct tu ur re e C Co or re e A Ar re ea a P Po ow we er r@ @V VG GA A P Po ow we er r@ @1 10 08 80 0p p P Po ow we er r@ @M [21], [24], [16], [20], [23], [28], [26], [19], [27]. The power results reported by [30] are obtained by their own tool (similar to SPICE) using switching activities from 6 different MPEG videos.…”

Section: A Comparison With Related Workmentioning

confidence: 99%

Evaluating the Impact of Architectural Decisions on the Energy Efficiency of FDCT/IDCT Configurable IP Cores

Livramento

¹

,

Moraes²,

Machado³

et al. 2020

JICS

3

0

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The development of mobile multimedia devices follows the platform-based design methodology in which IP cores are the building blocks. In the context of mobile devices there is a concern of battery lifetime which leads to the need of energy-efficient IP cores. This paper presents four energy-efficient FDCT/IDCT configurable IP cores. These architectures are based on Massimino’s algorithm, which was chosen due to its high accuracy and parallelism. The four architectures were built by combining fully-combinational or pipelined datapaths, using either a single or two 1-D DCT blocks with a transpose buffer that assures the optimal minimum latency of eight cycles. Synthesis results for 90nm showed that our most efficient architecture, which uses two pipelined 1-D blocks, achieved 250 MHz as maximum frequency at a total power of 14.03 mW. Such frequency was enough to process 16x 1080p@30fps videos in real time (nearly 2 GigaPixels/s). Comparisons with related work, in terms of energy efficiency (μJ/MPixels), revealed that our most energy-efficient architecture is at least 2 times as efficient as other DCT architectures. Moreover, the four designed architectures were also synthesized by using common low-power techniques. These results showed that pipelined versions at high throughput tend to take more benefit from using Low-Vdd and High-Vt combined than the combinational ones, thus becoming the most energy efficient.

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Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation

Cited by 4 publications

References 19 publications

An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms

An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms

A novel VLSI linear array for 2-D DCT/IDCT

Evaluating the Impact of Architectural Decisions on the Energy Efficiency of FDCT/IDCT Configurable IP Cores

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