Memory-fast computer memories

Ng, Richard Yew Fatt

doi:10.1109/6.158634

Cited by 9 publications

(2 citation statements)

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“…The increase in the ratio of memory cycle time to processor cycle time has motivated the development of innovative memory technologies 24,21]. The one approach we examine here is page-mode DRAM access.…”

Section: Block Transfersmentioning

confidence: 99%

Performance evaluation of hierarchical ring-based shared memory multiprocessors

Holliday

Stumm

1994

IEEE Trans. Comput.

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This paper investigates the performance of word-packet, slotted unidirectional ring-based hierarchical direct networks in the context of large-scale shared memory multiprocessors. Slotted unidirectional rings are attractive because their electrical characteristics and simple interfaces allow for fast cycle times and large bandwidths. For large-scale systems, it is necessary to use multiple rings for increased aggregate bandwidth. Hierarchies are attractive because the topology ensures unique paths between nodes, simple node interfaces and simple interring connections. To ensure that a realistic region of the design space is examined, the architecture of the network used in the Hector prototype is adopted as the initial design point. A simulator of that architecture has been developed and validated with measurements from the prototype. The system and workload parameterization re ects conditions expected in the near future. The results of our study show the importance of system balance on performance. Large-scale systems inherently have large communication delays for distant accesses, so processor e ciency will be low, unless the processors can operate with multiple outstanding transactions using techniques such as prefetching, asynchronous writes and multiple hardware contexts. However with multiple outstanding transactions and only one memory bank per processing module, memory quickly saturates. Memory saturation can be alleviated by having multiple memory banks per processing module, but this shifts the bottleneck to the ring subsystem. While the topology of the ring hierarchy a ects performance | we show that topologies with a similar branching factor at all levels, except, possibly, for slightly smaller rings at the root of the hierarchy tend to perform best | the ring subsystem will inherently limit the throughput of the system. Hence increasing the number of outstanding transactions per processor beyond a certain point only has a limiting e ect on performance, since it causes some of the rings to become congested. An adaptive maximum number of outstanding transactions appears necessary to adjust for the appropriate tradeo between concurrency and contention as the communication locality changes. We show the relationships between processor, ring and memory speeds, and their e ects on performance. Using block transfers for prefetching seems unlikely to be advantageous in that the improvement in the cache hit ratio needed to compensate for the increased network utilization is substantial.

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Section: Block Transfersmentioning

confidence: 99%

Performance evaluation of hierarchical ring-based shared memory multiprocessors

Holliday

Stumm

1994

IEEE Trans. Comput.

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“…Therefore, SDRAM devices are not truly random access memory and have nonuniform access latencies. There are enhanced DRAM devices, such as CDRAM and EDRAM [9,48], which have an SRAM cache on the DRAM chip to reduce access latency, especially row conflict latency. Unlike the sense amplifiers of JEDEC DRAM, whose contents are lost during a bank precharge, the row data can still be accessed from the SRAM cache when the enhanced DRAM device is being precharged [72].…”

Section: Sdram Access Latencymentioning

confidence: 99%