Memory Issues in Embedded Systems-on-Chip

Panda, Preeti Ranjan; Dutt, Nikil; Nicolau, Alexandru

doi:10.1007/978-1-4615-5107-2

Cited by 159 publications

(101 citation statements)

References 21 publications

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“…A branch and bound algorithm to solve the hardware/software partitioning problem with pipelined scheduling was introduced in [5]. Panda et al [6,7] published a comprehensive technique to SPMs allocation on a single processor to reduce the run time through maximally utilizing the available fast SPM memory. Integer linear programming approaches to optimally solve the memory allocation problem for SPMs were presented in [8,9].…”

Section: Related Workmentioning

confidence: 99%

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

Salamy¹,

Sopeju²

2014

IJCA

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As the utilization of multiprocessors system-on-chip (MPSoC) is becoming ubiquitous, demands for effective allocation and scheduling techniques are needed more than ever to harness the power of MPSoCs. An MPSoC is a system consisting of multiple heterogeneous processing cores, memory hierarchies, and communication infrastructure to effectively overcome the power and clock constraints from single core architectures. MPSoCs provide the performance demanded by embedded applications especially real-time multimedia applications. This article presents effective techniques to partitioning the processing cores and memory budget in an MPSoC among multiple embedded applications possibly entering the system at different times. The proposed framework will study the structure of each application and predict the possible reduction in schedule time if more processors and/or memory budget are assigned to this application. The objective is to fairly divide the resources such that the schedule times for the applications are minimized. Results on different embedded applications workloads and under different system resources show the effectiveness of our techniques that were able to reduce the cycle count by 10.2 % on average compared to an effective technique in the literature.

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Section: Related Workmentioning

confidence: 99%

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

Salamy¹,

Sopeju²

2014

IJCA

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“…(b) The scratch pad memory [14]. The scratch pad memory serves as a local memory for quickly loading data in the CGRA's PEs.…”

Section: Cgra Architecture Descriptionmentioning

confidence: 99%

Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures

Dimitroulakos

Galanis

Goutis

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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“…Panda et al [15] presented an efficient use of a memory hierarchy by placing the most commonly used variables onto the scratchpad. The dynamic copying of array parts was studied in [5].…”

Section: Related Workmentioning

confidence: 99%

Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization

Falk

Verma

2004

Software and Compilers for Embedded Systems

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Abstract. For mobile embedded systems, the energy consumption is a limiting factor because of today's battery capacities. Besides the processor, memory accesses consume a high amount of energy. The use of additional less power hungry memories like caches or scratchpads is thus common. This paper presents a combined approach for energy consumption minimization consisting of two complementary and phase-coupled optimizations, viz. data partitioning and loop nest splitting. In a first step, data partitioning partitions large arrays found in typical embedded software into smaller ones which are placed onto an on-chip scratchpad memory. Although being effective w. r. t. energy dissipation, this optimization adds overhead to the code since the correct part of a partitioned array has to be selected at runtime. Therefore, the control flow is optimized as a second step in our framework. In this phase, loop nests containing if-statements are split using genetic algorithms leading to minimized if-statement executions. However, loop nest splitting leads to an increase in code size and can potentially annul the program layout achieved by the first step. Consequently, the proposed approach iteratively applies these optimizations till a local optimum is found. The proposed framework of combined memory and control flow optimization leads to considerable energy savings for a representative set of typical embedded software routines. Using an accurate energy model for the ARM7 processor, energy savings between 20.3% and 43.3% were measured.

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Memory Issues in Embedded Systems-on-Chip

Cited by 159 publications

References 21 publications

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures

Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization

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