2018 IEEE International Symposium on Workload Characterization (IISWC) 2018
DOI: 10.1109/iiswc.2018.8573527
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Memory Requirements for Convolutional Neural Network Hardware Accelerators

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Cited by 57 publications
(20 citation statements)
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“…Most of the architectures that are used in the literature have many layers and, hence, huge numbers of parameters to store and compute. The ResNet50 architecture has 53 convolutions and one fully connected layer with over 23 million trainable parameters [ 108 ]. performed a detailed analysis on the memory requirements of each model before and after deployment in a hand-held device chip.…”
Section: Discussion and Future Directionmentioning
confidence: 99%
“…Most of the architectures that are used in the literature have many layers and, hence, huge numbers of parameters to store and compute. The ResNet50 architecture has 53 convolutions and one fully connected layer with over 23 million trainable parameters [ 108 ]. performed a detailed analysis on the memory requirements of each model before and after deployment in a hand-held device chip.…”
Section: Discussion and Future Directionmentioning
confidence: 99%
“…The experimental analysis shows that this method saves 98% memory as compared to traditional CNN. It also indicates that this methods saves more than 90% of memory compared to state-of-the-art related to Virtual DNNs ( vDNNs) [13]…”
Section: Memory-schedulingmentioning
confidence: 98%
“…One of the most well adopted paradigms are the single computation engines [8]- [16], due to their balanced trade-off of programmability and performance. Currently, despite the progress in processing unit design, further gain in the attainable performance of such engines is hindered by two main factors: i) memory-bound layers that are dominated by the communication with the external memory [13]- [15], [57]. While embedded platforms provide limited bandwidth [58]- [60], e.g.…”
Section: Challenges Of Fpga-based Cnn Inference Enginesmentioning
confidence: 99%