Memory window engineering of Ta2O5−x oxide-based resistive switches via incorporation of various insulating frames

Abstract

Three-dimensional (3D) stackable memory frames, including nano-scaled crossbar arrays, are one of the most reliable building blocks to meet the demand of high-density non-volatile memory electronics. However, their utilization has the disadvantage of introducing issues related to sneak paths, which can negatively impact device performance. We address the enhancement of complementary resistive switching (CRS) features via the incorporation of insulating frames as a generic approach to extend their use; here, a Pt/Ta2O5−x/Ta/Ta2O5−x/Pt frame is chosen as the basic CRS cell. The incorporation of Ta/Ta2O5−x/Ta or Pt/amorphous TaN/Pt insulting frames into the basic CRS cell ensures the appreciably advanced memory features of CRS cells including higher on/off ratios, improved read margins, and increased selectivity without reliability degradation. Experimental observations identified that a suitable insulating frame is crucial for adjusting the abrupt reset events of the switching element, thereby facilitating the enhanced electrical characteristics of CRS cells that are suitable for practical applications.

Capacitive and RRAM Forming-Free Memory Behavior of Electron-Beam Deposited Ta2O5 Thin Film for Nonvolatile Memory Application

“…Among the various metal oxides, transition metal oxides (TMOs) such as WO 3 , Gd 2 O 3 , CeO 2 , HfO 5 , MnO, NiO, and Ta 2 O 5 have shown superior RS phenomenon, with good stability, low power consumption, and constant switching characteristics . Ta 2 O 5 being a high dielectric constant (∼25) with good chemical and physical properties has shown viable RS properties and capacitive memory. − In addition, NVM devices based on Ta 2 O 5 have an encouraging electrical performance, including high switching speed, high endurance, and forming-free resistive switching. However, the possibility of forming-free RS memory resulting from the high dielectric constant ( k ) Ta 2 O 5 TF is less explored, making it an excellent choice to study its resistive switching characteristics and capacitive memory.…”

Selectively biased tri-terminal vertically-integrated memristor configuration

“…Increased integration density, which resulted from incorporation in circuits, uncovered issues which impede nominal device operation, such as sneak path currents. A popular mitigation strategy has been the usage of new topologies, such as complementary resistive switching (CRS) [5], 1 selector 1 memristor (1S1M) [6], 1 diode 1 memristor (1D1M) [7] configurations. Other theoretical propositions include using a complementary memristor array composed by two antiserially connected memristors [8].…”

Selectively biased tri-terminal vertically-integrated memristor configuration

“…Increased integration density, which resulted from incorporation in circuits, uncovered issues which impede nominal device operation, such as sneak path currents. A popular mitigation strategy has been the usage of new topologies, such as complementary resistive switching (CRS) 7 , 1 selector 1 memristor (1S1M) 8 , 1 diode 1 memristor (1D1M) 9 configurations. Other theoretical propositions include using a complementary memristor array composed by two anti-serially connected memristors 10 .…”