Memristor-Based Loop Filter Design for Phase Locked Loop

Adesina, Naheem Olakunle; Srivastava, Ashok

doi:10.3390/jlpea9030024

Cited by 19 publications

(2 citation statements)

References 23 publications

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“…8, the measured phase noise is -122 dBc/Hz at 1 MHz offset frequency and -126 dBc/Hz at 10 MHz offset frequency. This shows an improvement in phase noise performance when compared to the work in [20,21].…”

Section: B Mos2 Tfet Ring Oscillatormentioning

confidence: 68%

Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

Adesina

2021

Preprint

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This paper presents the design of an inverter, half adder, and ring oscillator using compact models of MoS2 channel-based tunnel field effect transistor (TFET). The TFET models (both n and p-type) are written in high-level hardware language Verilog-Analog (Verilog-A) following the analytical model of [1] and the output characteristics of the components are simulated in Cadence/Spectre software. The performance of the designed inverter (a basic building block of VLSI circuit) is analyzed by extracting its different parameters, such as transfer characteristics, power dissipation and consumption, delay, power delay product. The simulated outputs (sum & carry) obtained from the half adder circuit exactly match the truth table of the circuit. Moreover, our observation reveals that the ring oscillator can operate at a higher frequency with lower power consumption in comparison to the existing CMOS and GFET technologies. We have also reported an improvement to the limiting factor of ring oscillator performance i.e. phase noise at two different offset frequencies. With all the output characteristics obtained from the commercial software simulation, we expect our model to be applicable to a real-time low-power VLSI circuit.

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Section: B Mos2 Tfet Ring Oscillatormentioning

confidence: 68%

Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

Adesina

2021

Preprint

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“…4d, the measured phase noise is -122.5 dBc/Hz at 1 MHz offset frequency and -126 dBc/Hz at 10 MHz. This shows an improvement in phase noise performance when compared to the work in [19,20]…”

Section: Mos2 Tfet Ring Oscillatormentioning

confidence: 69%

Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

Adesina

Srivast

et al. 2021

Preprint

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This paper presents a newly designed physics-based analytical current transport model of both n- and p-type MoS2 tunnel field-effect transistor (TFET) using a high-level hardware language Verilog-Analog (Verilog-A) within Cadence/Spectre. The performance of our model is analysed by extracting different parameters, including transfer characteristics, power dissipation, and consumption, delay, power delay product (PDP) from the designed inverter. Moreover, we design a ring oscillator, and a half adder circuit to assess the compatibility of our model in both the analog and digital circuits. Our observation reveals that the voltage-controlled oscillator (VCO) can operate at a frequency of 31.6 GHz with a power consumption of 0.083 mW, and generates a phase noise of -122.5 dBc/Hz at 1MHz offset frequency. The simulated outputs (sum & carry) obtained from the half adder circuit exactly match the truth table of the circuit. Last, we present a comparison, using the performance parameters, of the ring oscillator with existing CMOS and GFET technologies. The results show that our designed VCO oscillates at a higher frequency with low power consumption and improved phase noise performance. With all the output characteristics obtained from the commercial software simulation, we expect our model to be applicable to a real-time low power VLSI circuit.

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Design and implementation of an efficient memristor-based chaotic circuit

Kumari,

Yadav

2023

Int. j. inf. tecnol.

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Memristor-Based Loop Filter Design for Phase Locked Loop

Cited by 19 publications

References 23 publications

Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

Design and implementation of an efficient memristor-based chaotic circuit

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