Memristor−CMOS Hybrid Integrated Circuits for Reconfigurable Logic

Abstract

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Observation of conducting filament growth in nanoscale resistive memories

“…N anoscale resistive switching devices are typically based on two-terminal metal/insulator/metal (MIM) structures and have been extensively studied as a leading candidate for non-volatile memory [1][2][3][4] and reconfigurable logic [5][6][7][8] applications. Recently, they have also been linked to the concept of memristors [9][10][11] for analogue circuit 12 and neuromorphic computing [13][14][15] applications.…”

Anatomy of a Nanoscale Conduction Channel Reveals the Mechanism of a High‐Performance Memristor

“…Moreover, these devices have also exhibited signifi cant potential in other applications, such as stateful logic operations, [ 40 ] neuromorphic computing, [ 27 , 41 ] and CMOS/memristor hybrid circuits for confi guration bits and signal routing. [ 42 ] However, as pointed out by the ITRS 2010, there are still challenges remaining for these devices, among which are reliability and a better understanding of the microscopic picture of the switching. [ 1 ] The reliability issue includes switching endurance, long-term thermal stability, repeatability, and robustness of the conduction channel, [ 1 ] all of which depend on the chemical and structural details of the conduction channel revealed in this study.…”

Toward exascale computing through neuromorphic approaches.

“…The polarities are opposite (doped-undoped, undoped-doped) in order to facilitate the neuromorphic characteristic of the curve shown in Figure 2. The interval Pt leads are all tied together on each row of the array, and addressing occurs through simultaneous voltages being applied at either the top/bottom Pt lead and the interval lead, similar to the scheme shown by Xia et al [13].…”