Mesh-Structure-Enabled Programmable Multitask Photonic Signal Processor on a Silicon Chip

Abstract

Photonic integrated circuits (PICs) have recently attracted extensive attention in advanced photonic signal processing to meet the ever-increasing demands on high-speed and ultracompact data signal management. However, programmable and multitask photonic signal processing is still full of challenges, especially the scalable photonic integration solution. Here, we design, fabricate, and demonstrate a mesh-structure-enabled programmable multitask photonic signal processor on a silicon chip. It relies on a scalable 2D mesh structure network with a number of hexagonal unit cells formed by building blocks of tunable Mach–Zehnder interferometers (MZIs). We study several simple and complex optical filtering functions using configured single ring resonator, cascaded ring resonators, ring-assisted MZI, cascaded MZIs, reconfigurable and tunable comb filter and (de)­interleaver, and double-injection ring resonators. For the proof-of-concept demonstration of on-chip programmable multitask photonic signal processing, a monolithically integrated silicon chip with four hexagonal unit cells is fabricated with greatly reduced geometric dimension. By appropriately adjusting the thermo-optic phase shifters of MZIs, versatile programmable multitask photonic signal processing functions are demonstrated in the experiment with impressive performance, including single ring resonator, cascaded ring resonators, asymmetric MZI, ring-assisted MZI, optical delay line, multiport router, and N × N optical switch. In particular, we also demonstrate the optical interference unit (OIU)-enabled self-configurable router and switch and their practical applications in fiber-optic communication systems. The demonstrations may open up new perspectives for on-chip solutions to ultracompact, reconfigurable, programmable, and multifunctional data signal management in advanced optical communication networks.

Reconfigurable Low-Threshold All-Optical Nonlinear Activation Functions Based on an Add-Drop Silicon Microring Resonator

“…Compared with the MZI-based structures and the Ge/Si-based structures, the proposed add-drop MRR has a smaller footprint, a lower nonlinear threshold, and a lower fabrication complexity. In order to tune the parameters of the NAFs, a planar directional coupler structure [41], or a TO-tuned MZI [42][43][44][45] can be integrated in the MRR, where the coupling coefficient of the MRR can be tuned flexibly. By tuning the coupling coefficient, the Q factor of the MRR can be changed, and the threshold of the NAFs can be changed accordingly.…”

Lithium Niobate Piezoelectric Actuator-Integrated Fiber Fabry-Pérot Tunable Filter with Ultrahigh Speed and Linearity

“…High-speed wavelength tuning is essential for optical fiber communication, 1,2 microwave photonics, 3−5 lasers, 6−8 spectroscopy, 9−11 sensors interrogation, 12 and many other fields, where tunable filters are key elements. The Fabry-Peŕot tunable filter (FPTF) is a versatile and reliable modulation approach with a high resolution and low optical insertion loss.…”

“…High-speed wavelength tuning is essential for optical fiber communication, , microwave photonics, − lasers, − spectroscopy, − sensors interrogation, and many other fields, where tunable filters are key elements. The Fabry-Pérot tunable filter (FPTF) is a versatile and reliable modulation approach with a high resolution and low optical insertion loss. , The mechanism of FPTF includes refractive index tuning, such as electro–optical and liquid–crystal tuning, , as well as cavity-length tuning, such as mechanical, electrostatic, , and piezoelectric tuning. , …”

Efficient stochastic parallel gradient descent training for on-chip optical processor

“…What' s more, it has also been reported to undo the crosstalk caused by mode mixing in multi-mode waveguide 38 , FMF 39,40 or MZI 29 mesh automatically and get better signal quality after optimization. However, most existing integrated linear optical processor or optical neural networks (ONNs) are implemented by pre-training the weights of the matrix in electronic computer and adjusting the phase shifter voltage according to the training result, which is very inefficient 16,30 . Additionally, due to external disturbance, thermal crosstalk inside the chip and fabrication tolerance of the complementary metal oxide semiconductor (CMOS) process, there is always a certain difference between the actual matrix of the integrated photonic chip and the target matrix, which will increase geometrically as the size of the chip increases.…”