Metal∕Dielectric Liner Formation by a Simple Solution Process for through Silicon via Interconnection

Abstract

We investigated the formation of metal and dielectric liners in via holes. We obtained a conformal deposition of the Ag metal and PVPh liners in Si deep via holes. The measured Ag liner thickness increased from 0.18 μm to 1.44 μm as the radius of the via hole was increased from 0.85 μm to 5 μm. We also obtained a conformal deposition of the PVPh dielectric liner of about 830 nm in thickness in 10 μm deep via holes. The Ag metal and PVPh dielectric liners had uniform thickness on every region of their respective deep via holes.The emerging three-dimensional (3D) integration technology can form highly integrated systems by vertically stacking and connecting various materials, technologies and functional components. 1, 2 3D integration offers high interconnection density and the use of short wire lengths and small chips. At this time, through silicon via (TSV) is more attractive than other 3D interconnection methods because it offers a way to solve interconnection problems while providing integrated functions for higher performance of the integrated system. 3 The 3D TSV process in the front end of line process (FEOL) is divided into via etching, insulator and barrier deposition, seed layer deposition, metal filling and chemical mechanical polishing (CMP). 3 The conformal depositions of the insulator, barrier and seed layer are important for obtaining stable electrical isolation, uniform metal filling and high quality diffusion barrier.The formations of metal seed layer and metal liner in TSV process is performed by using the Cu metal source, because it is a low cost material. However, the Cu etching is very difficult process. Therefore, the patterning process of Cu is also very difficult task for electrical isolation. Meanwhile, Ag has recently attracted a great interest as a potential candidate for advanced ultra large scale integrated circuit (ULSI) metallization, due to the conductivity of Ag is about 7 percent higher than for Cu. Moreover, Ag is possible to pattering process for electrical isolation.To form the seed and barrier layers, sputtering or chemical vapor deposition (CVD) have been normally employed. 4, 5 Between the two methods, sputtering deposition is preferred over CVD deposition, because it is a more cost-effective process. However, sputter deposited films have very poor uniformity and stack-coverage inside via holes, especially inside high aspect ratios (ARs) via holes. 6,7 Meanwhile, the plasma-enhanced chemical vapor deposition (PECVD) method and the atmospheric-pressure CVD (APCVD) method are widely used for the formation of dielectric films. However, deposited dielectric layer have some problems, such as a low step coverage and high leakage current. On the other hand, the low-pressure CVD (LPCVD) method is used to form dielectric layers of highstep-coverage and low leakage current, but it requires a high process temperature. 8 Moreover, this method has difficulty in depositing thin dielectric layers uniformly in high ARs via holes because its process parameters must be controlled carefully.As ...

Ruthenium Nanoparticles in Ionic Liquids – A Saga

“…Moreover, this alternative solution should produce the liners with reduced cost. Recently, results on the formation of metallic films by annealing of silica supported Cu NPs [116] and Ag [117] have been reported. ILs are ideal media to synthesise such metallic NPs, as they act in the process both as solvent and stabiliser [13].…”