Metal diffusion barriers for GaAs solar cells

Abstract

In this study accelerated ageing testing (AAT), J-V characterization and TEM imaging in combination with phase diagram data from literature are used to assess the potential of Ti, Ni, Pd and Pt as diffusion barriers for Au/Cu-based metallization of III-V solar cells. Ni barriers show the largest potential as at an AAT temperature of 250 • C both cells with 10 and 100 nm thick Ni barriers show significantly better performance compared to Au/Cu cells, with the cells with 10 nm Ni barriers even showing virtually no degradation after 7.5 days at 250 • C (equivalent to 10 years at 100 • C at an E a of 0.70 eV). Detailed investigation shows that Ni does not act as a barrier in the classical sense, i.e. preventing diffusion of Cu and Au across the barrier. Instead Ni modifies or slows down the interactions taking place during device degradation and thus effectively acts as an 'interaction' barrier. Different interactions occur at temperatures below and above 250 • C and for thin (10 nm) and thick (100 nm) barriers. The results of this study indicate that 10-100 nm thick Ni intermediate layers in the Cu/Au based metallization of III-V solar cells may be beneficial to improve the device stability upon exposure to elevated temperatures.

The effect of high temperatures on the electrical characteristics of Au/n-GaAs Schottky diodes

“…The I-V and C-V investigations were carried out in two modes: (1) during annealing, conducted at some elevated temperature in the 80 -480 K range in 20 K steps, and (2) post annealing measurements, conducted at 300 K after the annealing described in (1). Once the correct annealing temperature was established, a further 5 minutes was allowed for the system to establish equilibrium.…”

“…At present it is used for many applications such as solar cells in space, sources and detectors in optical fibres and as microwave sources [1][2][3]. The high electron mobility and high carrier saturation velocity of the material makes it ideally suited for the fabrication of high frequency and low power devices [4].…”

Adsorption and interface reaction in direct active bonding of GaAs to GaAs using Sn–Ag–Ti solder filler

“…In the field of integrated circuit manufacturing, gallium arsenide (GaAs) is one of the most commonly used substrate materials [1][2][3]. Owing to its superior electrical performance and optical properties, it presents in a wide range of applications from optical devices to high speed digital circuits and microwave devices [4][5][6].…”

Controlled Growth of Heterostructured Ga/GaAs Nanowires with Sharp Schottky Barrier

“…15−18 Inevitably, when configured into NW devices, this pinning would make the contact barrier between NWs and metals being independent of the metal work function; therefore, special attention is required for the metallization of these NWs. 19,20 For example, InAs NWs typically have their surface Fermi level pinned in the conduction band, yielding a great challenge to achieve efficient contacts to their p-type NWs, which necessitates a surface InP remote doping strategy there. 21,22 As a result, it is technologically difficult to investigate and implement the effective nanoscale contact with III−V semiconductor NWs.…”

“…Because of their appropriate direct band gaps and remarkably high carrier mobilities, III–V compound semiconductor nanowires (NWs), such as gallium arsenide (GaAs) and indium arsenide (InAs), are widely investigated for various applications in next-generation electronics, optoelectronics, and others. − In particular, both intrinsic and axially or laterally p/n doped NWs are successfully synthesized by the catalytic vapor–liquid–solid (VLS) and/or vapor–solid–solid (VSS) mechanisms utilizing molecular beam epitaxy (MBE), − metal–organic chemical vapor deposition (MOCVD), − laser ablation, etc . However, since these NW materials have the relatively large surface-to-volume ratio with a significant amount of surface dangling bonds, all these unsaturated bonds would contribute a substantial amount of surface states, inducing the serious surface Fermi level pinning. − Inevitably, when configured into NW devices, this pinning would make the contact barrier between NWs and metals being independent of the metal work function; therefore, special attention is required for the metallization of these NWs. , For example, InAs NWs typically have their surface Fermi level pinned in the conduction band, yielding a great challenge to achieve efficient contacts to their p-type NWs, which necessitates a surface InP remote doping strategy there. , As a result, it is technologically difficult to investigate and implement the effective nanoscale contact with III–V semiconductor NWs.…”