Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications

Kaur, Ravneet; Aggarwal, Sandeep Kr; Gupta, Mridula; Gupta, R. S.

doi:10.5573/jsts.2010.10.1.066

JSTS:Journal of Semiconductor Technology and Science

2010

DOI: 10.5573/jsts.2010.10.1.066

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Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications

Ravneet Kaur¹,

Sandeep Kr Aggarwal²,

Mridula Gupta³

et al.

Abstract: Abstract-Improvement in breakdown voltage (BV ds)

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Cited by 5 publications

References 33 publications

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A Novel Spiral-Type Motion Estimation Architecture for H.264/AVC

Hirai

Song²,

Liu³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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Abstract-New features of motion compensation, such as variable block size and multiple reference frames are introduced in H.264/AVC. However, these new features induce significant implementation complexity increases. In this paper, an efficient architecture for spiral-type motion estimation is proposed. First, we propose a hardware-friendly spiral search order. Then, an efficient processing element (PE) architecture for ME is proposed to achieve the proposed search order. The improved PE enables one-pixel-move of the reference pixel data to top, bottom, right, and left by four ports for input and output. Moreover, the parallel calculation architecture to calculate all block size with the SAD of 4x4 is introduced in the proposed architecture. As the result of hardware implementation, the hardware cost is about 145k gates. Maximum clock frequency is 134 MHz in the case of FPGA (Xilinx Vertex5) implementation.

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A Novel Spiral-Type Motion Estimation Architecture for H.264/AVC

Hirai

Song²,

Liu³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

Inter-Pin Skew Compensation Scheme for 3.2-Gb/s/pin Parallel Interface

Lee¹,

Kim²,

Nam³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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Abstract-An inter-pin skew compensation scheme is proposed, which minimizes the inter-pin skew of parallel interface induced by unequal trace length and loading of printed circuit board (PCB). The proposed scheme measures the inter-pin skew and compensates during power-up with simple hardware. The proposed scheme is applied to 3.2-Gb/s/pin DDR4 SDRAM and implemented in a 0.18 m CMOS process. The inter-pin skew is compensated in 324-cycles of 400-MHz clock and the skew is compensated to be less than 24-ps.

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Fast Circuit Simulation Based on Parallel-Distributed LIM using Cloud Computing System

Inoue¹,

Sekine²,

Hasegawa³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications

Abstract: Abstract-Improvement in breakdown voltage (BV ds)

Cited by 5 publications

References 33 publications

A Novel Spiral-Type Motion Estimation Architecture for H.264/AVC

A Novel Spiral-Type Motion Estimation Architecture for H.264/AVC

Inter-Pin Skew Compensation Scheme for 3.2-Gb/s/pin Parallel Interface

Fast Circuit Simulation Based on Parallel-Distributed LIM using Cloud Computing System

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