Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Buccella, Pietro; Stefanucci, Camillo; Zeng, Hao; Moursy, Yasser; Iskander, Ramy; Sallèse, Jean-Michel; Kayal, Maher

doi:10.1109/tcad.2015.2513008

Cited by 17 publications

(9 citation statements)

References 35 publications

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“…In the context of European Project AUTOMICS [6] with 7th framework entitled "Pragmatic Solution for Parasitic-Immune Design of Electronics ICs for automotive", we aim at proposing a new pragmatic, focused and well-structured solution for modeling of parasitic coupling in automotive ICs [7] [8].…”

Section: Modeling Methodologymentioning

confidence: 99%

Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology

Zeng

Moursy

Iskander

et al. 2016

IEEE Trans. Circuits Syst. I

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Smart Power integrated circuits receive an increasing attraction recently, especially in automotive industry. Substrate noise coupling is one of the major causes of failure in this kind of integrated circuits that requires circuit redesign and increases the overall cost. An exhaustive failure analysis is needed to identify failures due to substrate coupling. In this paper, we present a post-layout extraction and simulation methodology for substrate parasitic modeling. Based on this methodology, we have developed a dedicated Computer-Aided-Design tool that is used for substrate extraction from layout patterns. The extraction employs a meshing algorithm for substrate parasitic generation.To validate the substrate model, the process of benchmarking uses industrial design structures in 0.35µm high-voltage-CMOS technology. Two test cases in transient simulation are considered in this work. The first one is a common used current mirror circuit. Our tool predicts the interference of substrate currents to this basic circuit. The second test case is an industrial design test-chip where parasitic coupling is investigated in a standard automotive test. Eventually, by using the proposed CAD tool, it becomes possible to simulate the behaviors of substrate noise at early phase before fabrication.

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Section: Modeling Methodologymentioning

confidence: 99%

Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology

Zeng

Moursy

Iskander

et al. 2016

IEEE Trans. Circuits Syst. I

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“…Along with the experimental research, semiconductor-based FET modeling and simulation serve as a bridge between manufacturers and designers [ 179 , 180 ] and provide essential tools to explore the fundamental properties of 2D TMDCs for the device applications [ 181 ]. Various softwares (such as PHILIPAC, SLIC, and SPICE) are available to model and investigate the devices [ 182 , 183 ]. These compact models for TMDC-based FETs are vital to study the device behaviors with computational efficiency and accuracy without loss of the physical insights [ 184 ].…”

Section: Field-effect Transistorsmentioning

confidence: 99%

Two-Dimensional Transition Metal Dichalcogenides and Their Charge Carrier Mobilities in Field-Effect Transistors

2017

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Two-dimensional (2D) materials have attracted extensive interest due to their excellent electrical, thermal, mechanical, and optical properties. Graphene has been one of the most explored 2D materials. However, its zero band gap has limited its applications in electronic devices. Transition metal dichalcogenide (TMDC), another kind of 2D material, has a nonzero direct band gap (same charge carrier momentum in valence and conduction band) at monolayer state, promising for the efficient switching devices (e.g., field-effect transistors). This review mainly focuses on the recent advances in charge carrier mobility and the challenges to achieve high mobility in the electronic devices based on 2D-TMDC materials and also includes an introduction of 2D materials along with the synthesis techniques. Finally, this review describes the possible methodology and future prospective to enhance the charge carrier mobility for electronic devices.

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“…A reduction mechanism is used to filter out the layers that do not contribute in the substrate parasitic coupling such as metal and poly-silicon layers. This reduction is essential to simplify the extracted netlist meanwhile keeping the most relevant information for the parasitic coupling analysis [10]. An adaptive meshing strategy is used to reduce the number of the components [11].…”

Section: Automics: Pragmatic Substrate Parasitic Extraction Framementioning

confidence: 99%

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Moursy

Zeng

Khalil

et al. 2017

IEEE Trans. Power Electron.

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Abstract-This paper presents a methodology to analyze the substrate noise coupling and reduce their effects in smart power integrated circuits. This methodology considers the propagation of minority carriers in the substrate. Hence, it models the lateral bipolar junction transistors that are layout dependent and are not modeled in conventional substrate extraction tools. It allows the designer to simulate substrate currents and check their effects on circuits functionality. The proposed methodology employs a dedicated tool for substrate network generation referred to as AUTOMICS. We applied the methodology on two test cases. The first case is a DC-DC buck converter chip fabricated with a 0.35 µm HV-CMOS technology. The DC coupling current between the switches and the bandgap circuit is simulated and verified with measurements. The second test case is an automotive industrial chip that has a latch-up failure due to substrate coupling. In transient simulations, the failure has been reproduced as in measurements. This highlights the stronghold of the methodology since it can be used to prevent this type of failures before fabrication. The proposed methodology can reduce the number of redesigns in the automotive industry. Hence, it shortens the time-to-market, improves the robustness of the design, and reduces the cost.

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Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Cited by 17 publications

References 35 publications

Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology

Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology

Two-Dimensional Transition Metal Dichalcogenides and Their Charge Carrier Mobilities in Field-Effect Transistors

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

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