Methods for improving transition delay fault coverage using broadside tests

Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan

“…However, recent interest in achieving high delay test coverage from scan based tests, beyond what is possible from traditional LOC tests, to detect small delay defects and perhaps also avoid the need for at-speed functional tests, has revived interest in such schemes [10]. In this paper we investigate a strategy for realizing most of the TDF coverage gains achievable from enhanced scan at a fraction of the cost by implementing partial enhanced scan designs.…”

“…Such signals must be avoided in any low cost design which attempts cost savings from a partial enhanced scan methodology. The need for a high speed scan enable is alleviated in the dual flip-flop enhanced scan design in [10], where the enhanced scan flip-flop comprises two cascaded standard scan flip-flops as shown in Figure 5. Here, while Scan Enable 1 is in the shift mode (high) to shift and launch V2 at the launch clock edge, Scan Enable 2 is set to the functional mode (low) to capture the response in FF2.…”

“…To keep down costs it is also critically important to avoid the need for a high speed scan enable control signal. In Figure 5 we have presented a design from [10] of an enhanced scan flip-flop design that can achieve this, albeit using two slow global scan control signals. Figure 9 presents an alternative design, based on our recently proposed [12,13] Delay Test Scan Flip-Flop (DTSFF) that achieves the same capability.…”

“…Observe in this design that the redundant flip-flop that holds the V2 bit to be shifted in and launched at a MUX input is actually located in the standard cell in front of the functional flipflop. The advantage to the Enhanced DTSFF over the design in [10] is that it is comparable in hardware complexity to full enhanced scan design. The Enhanced DTSFF cell has identical pinout as compared to a standard multiplexer based scan flip-flop, and therefore it can be seamlessly integrated in industry standard design flows.…”

Functional and partially-functional skewed-load tests

“…This may not be acceptable when the long-term reliability of a chip is considered, since the same processes that lead to undetectable defects may cause circuit marginalities that will deteriorate with time and eventually cause the circuit to fail. The concern about low fault coverage for delay faults in general led to the development of design-for-testability techniques [6]- [7] as well as the use of several types of scan-based tests [7]- [8] in order to increase the delay fault coverage for a circuit. Specifically, skewed-load tests can be used in addition to broadside tests in order to improve the delay fault coverage.…”