Architectural restrictions of scan greatly limit the effectiveness of traditional scan based delay tests. It has been recently shown that additional testing for delays on short paths using fast clocks can significantly lower DPM. However, accurately obtaining the needed timing information for such tests from simulation is extremely difficult. The simulations must not only accurately account for the effects of process parameter variations, but also power supply noise and crosstalk from the excessive switching activity of scan tests. We suggest that learning signal timing information on silicon to "calibrate" such tests can be much more accurate and cost effective. However, such an approach requires that the outputs of the applied tests be hazard free to avoid learning incorrect timing due to a glitch at the output. Simulation results presented here indicate that such output hazard free test can be obtained with an average coverage only about 10 % below the transition delay fault coverage for both launch-on-shift (LOS) and launch-on-capture (LOC) modes.

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For nanometer designs, many subtle defects lead to excessive delays in signal paths that cause reliability concerns. Traditional test-based diagnosis methods can only identify the failing nodes without the capability to tell the defect nature behind the observed delay faults. This differentiation is important for gathering accurate defect statistics for process improvement during yield ramp-up. In this paper we presented an effective delay defect analysis methodology that can quickly categorize the delay defects into either transistor related defects or resistive interconnect defects. The new delay defect/failure characterization method is based on low voltage test and delay defect detection in slack interval (DDSI) method. Experimental results were presented to validate the effectiveness of the new method. Practical considerations were also addressed for adoption of the methodology.