Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing

Abstract

Architectural restrictions of scan greatly limit the effectiveness of traditional scan based delay tests. It has been recently shown that additional testing for delays on short paths using fast clocks can significantly lower DPM. However, accurately obtaining the needed timing information for such tests from simulation is extremely difficult. The simulations must not only accurately account for the effects of process parameter variations, but also power supply noise and crosstalk from the excessive switching activity of scan tests. We suggest that learning signal timing information on silicon to "calibrate" such tests can be much more accurate and cost effective. However, such an approach requires that the outputs of the applied tests be hazard free to avoid learning incorrect timing due to a glitch at the output. Simulation results presented here indicate that such output hazard free test can be obtained with an average coverage only about 10 % below the transition delay fault coverage for both launch-on-shift (LOS) and launch-on-capture (LOC) modes.

Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF

“…Then, by setting P min = T C 1 , we can meet the conditions of (1) and (2). In other words, the clock signal that satisfies the conditions of (1) and (2) is always present for every circuit.…”

“…Therefore, the proposed method can measure all sensitizable paths. We do not need to set P min = T C 1 while we need to decide T C 1 such that T C 1 satisfies (1) and (2). Considering process variations and the complexity of width controlling of clock signal, we should set T C 1 satisfying the two by a wide margin.…”

“…However, any delayed paths are detected. If T C 1 does not satisfy (2), the FF at the input of a path under measurement misses capturing transition, and then no transition is observed at the output of the path. Eventually, manufacturing testing fails detecting this fact.…”

“…Delay defects that degrade performance and cause timing related failures are emerging as a major problem in nanometer technologies [2]. Several delay fault models and delay test methods have been proposed.…”

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

“…Several delay fault models and delay test methods have been proposed. Transition fault and path delay fault are two prevalent fault models [2]. With the growing complexity of designs, scan-based techniques of testing are becoming very popular.…”