Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing

Xu, Gefu; Singh, A.D.

doi:10.1109/vlsid.2007.61

Cited by 19 publications

(7 citation statements)

References 12 publications

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“…1 show a fault free clock signal and the clock signal with a delay fault. We assume a typical LOC test [8], [9], where the shift clock rate is slow, and the launch and capture clock rate is fast (usually same as the system clock rate). The clock cycles in the scan-in and scan-out modes are longer than in the LOC mode.…”

Section: Fault Modelmentioning

confidence: 99%

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

Higami

Takahashi

Kobayashi

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper deals with delay faults on clock lines assuming the launch-on-capture test. In this realistic fault model, the amount of delay at the FF driven by the faulty clock line is such that the scan shift operation can perform correctly even in the presence of a fault, but during the system clock operation, capturing functional value(s) at faulty FF(s), i.e. FF(s) driven by the clock with delay, is delayed and correct value(s) may not be captured. We developed a fault simulator that can handle such faults and using this simulator we investigate the relation between the duration of the delay and the difficulty of detecting clock delay faults in the launchon-capture test. Next, we propose test generation methods for detecting clock delay faults that affect a single or two FFs. Experimental results for benchmark circuits are given in order to establish the effectiveness of the proposed methods.

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Section: Fault Modelmentioning

confidence: 99%

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

Higami

Takahashi

Kobayashi

et al. 2013

IEICE Trans. Inf. & Syst.

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“…Finally, adding circuitry to each SFF in order to generate a local fast scan enable signal has been proposed [35]. Six transistors are required per SFF, which represents a 10 to 15% SFF transistor count overhead.…”

Section: Los Emulation Strategiesmentioning

confidence: 99%

“…In summary, unlike DCDTS, all the LOS emulation strategies described above suffer from a systematic [7,13,34,35] or occasional [3,4] increase in test pattern count. Therefore, they cannot achieve simultaneous tester memory and test time reduction.…”

Section: Los Emulation Strategiesmentioning

confidence: 99%

Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

2011

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In this paper, we present a technique called Digital Captureless Delay Testing Sensors (DCDTS). This technique allows the detection of delay faults left uncovered by launchon-capture transitions due to excessive resources (mainly test time or tester memory) requirements, with top-off random launch-on-shift patterns that do not require fast switching scan enable signals. The DCDTS random patterns are internally generated, requiring virtually no additional test application time or tester memory. As such, DCDTS can be seen as a new way to save both test time and tester memory. Results show that DCDTS can achieve pattern volume and test time reduction factors of up to 3. When used in complement to existing compression techniques, DCDTS has the potential to triple their pattern volume (test application time) compression (reduction) rate. Area/performance overhead and technical obstacles to automation are minimal. An automated sensor selection procedure is proposed, with reasonable CPU time.

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“…• If a functional interconnect is used as a TAM, the scan enable signal must be generated in each test wrapper because functional interconnect protocols may not support scan enable signal. Therefore, in this paper, we assume that in each core scan enable signal is carefully routed like clock signal or is locally regenerated at each flip-flop using a technique such as Fast Scan Enable Generator [18] or Delay Test Scan Flip-Flop (DTSFF) [19] developed for scan-based delay testing so that capture operations can be performed at the full test clock speed.…”

Section: Assumptionsmentioning

confidence: 99%

Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing

Kundu

2008

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

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Conventional test access mechanism (TAM) and test wrappers of complex System-on-Chip (SoC) designs do not adequately utilize the system resources available in the functional mode of operation. With the advent of Network-on-Chip (NoC), the internal data transaction bandwidth has risen dramatically. This increase does not automatically translate to benefits during test. In this paper, we present a core test wrapper which takes advantages of the functional interconnect bandwidth to improve test application efficiency. Experimental results clearly demonstrate the benefit of the proposed approach in improving test application time.

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Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing

Cited by 19 publications

References 12 publications

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing

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