Methods for latent image simulations in photolithography with a polychromatic light attenuation equation for fabricating VIAs in 2.5D and 3D advanced packaging architectures

Abstract

As demand accelerates for multifunctional devices with a small footprint and minimal power consumption, 2.5D and 3D advanced packaging architectures have emerged as an essential solution that use through-substrate vias (TSVs) as vertical interconnects. Vertical stacking enables chip packages with increased functionality, enhanced design versatility, minimal power loss, reduced footprint and high bandwidth. Unlocking the potential of photolithography for vertical interconnect access (VIA) fabrication requires fast and accurate predictive modeling of diffraction effects and resist film photochemistry. This procedure is especially challenging for broad-spectrum exposure systems that use, for example, Hg bulbs with g-, h-, and i-line UV radiation. In this paper, we present new methods and equations for VIA latent image determination in photolithography that are suitable for broad-spectrum exposure and negate the need for complex and time-consuming in situ metrology. Our technique is accurate, converges quickly on the average modern PC and could be readily integrated into photolithography simulation software. We derive a polychromatic light attenuation equation from the Beer-Lambert law, which can be used in a critical exposure dose model to determine the photochemical reaction state. We integrate this equation with an exact scalar diffraction formula to produce a succinct equation comprising a complete coupling between light propagation phenomena and photochemical behavior. We then perform a comparative study between 2D/3D photoresist latent image simulation geometries and directly corresponding experimental data, which demonstrates a highly positive correlation. We anticipate that this technique will be a valuable asset to photolithography, micro- and nano-optical systems and advanced packaging/system integration with applications in technology domains ranging from space to automotive to the Internet of Things (IoT).

Design, Modeling, and Analysis of a 3-D Spiral Inductor With Magnetic Thin-Films for PwrSoC/PwrSiP DC-DC Converters

“…It should be mentioned that the equation in [55] is a first approximation. As reported in [56], the CD is a function of pillar length, photoresist chemistry, the exposure dose and the photomask feature geometry/size, wherein diffraction effects are very significant for rectangular/circular pillars.…”

“…× 100 µm interconnects as it is challenging to fabricate windings thicker than 100 µm [52], [56]. Increasing the conductor dimensions will lower the DC resistance, but this results in a longer reluctance path (longer flux path) and in turn a reduction in flux density.…”

Nondestructive monitoring of annealing and chemical–mechanical planarization behavior using ellipsometry and deep learning

“…In recent years, three-dimensional (3D) integrated circuit (IC) technology with the through-silicon via (TSV) has attracted significant attention because of its versatility, small size, and high performance. 3D IC is a technology that reduces the overall wire length and delay by vertically stacking multiple chips through high-density chip-to-chip interconnects [1][2][3][4][5][6][7] . TSV technology involves several processes, including etching holes in Si chips, depositing insulating/blocking/seeding layers, filling blind holes with Cu conductors, removing the backside Si and Cu overlay films via chemical-mechanical planarization (CMP) to expose Cu microcartridges, and ball bonding 8,9 .…”