Methods of accelerated characterization of VLSI cell libraries with prescribed accuracy control

Gavrilov, S. V.; Gudkova, O.N.; Egorov, Yu.B.

doi:10.1134/s1063739711070067

Cited by 7 publications

(2 citation statements)

References 2 publications

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“…However, setup time characterization for several cell sizes in a library is a tedious and iterative task, using large computational resources and time [2]. Due to Process, Supply voltage, and on-chip Temperature (PVT) variations, standard cell re-characterization at several PVT corners becomes necessary [3][4][5]. Further, as the technology is scaling down, the characterization of standard cell libraries is being done for a larger number of input transition time (T R ) and load capacitance (C L ) values, increasing computational time by a large amount [3].…”

Section: Introductionmentioning

confidence: 99%

“…Due to Process, Supply voltage, and on-chip Temperature (PVT) variations, standard cell re-characterization at several PVT corners becomes necessary [3][4][5]. Further, as the technology is scaling down, the characterization of standard cell libraries is being done for a larger number of input transition time (T R ) and load capacitance (C L ) values, increasing computational time by a large amount [3]. Hence, there is a need of accurate timing models that we can use in simplifying setup time characterization.…”

Section: Introductionmentioning

confidence: 99%

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Efficient static D-latch standard cell characterization using a novel setup time model

Sharma

Sharma²,

Dasgupta

et al. 2015

Sixteenth International Symposium on Quality Electronic Design

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In this paper we propose a simple setup time model for a transmission gate based static latch, which we later use to simplify standard cell library characterization methodology. We propose a simple model for the setup time which relates it linearly with input transition time (T R ) and load capacitance (C L ). We also derive the region of validity of our model in the T R , C L space. We derive the relationship of the model coefficients and the model's region of validity with the size of CMOS latch standard cell. We then derive simple expressions relating our model coefficients with the supply voltage, threshold voltage, and temperature variations. We use these relationships to simplify latch setup time characterization methodology, eliminating the necessity of about 67% HSPICE simulations. We show that our model and method of improving the characterization process are valid with the technology scaling and realistic input signals. We observe that the value of setup time obtained using our model based approach for latch characterization differ from their corresponding HSPICE based method by a maximum (average) of 3.2% (1.5%).

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