1995
DOI: 10.1016/0924-0136(95)01942-1
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Methods of analysing thermomechanical stress in plastic packages for integrated circuits

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Cited by 19 publications
(3 citation statements)
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“…The fabrication process of a complete packaged IC is a tricky one, as it involves the use of different materials of distinct coefficients of thermal expansion (CTEs), e.g. die bond pad, die attach adhesive/epoxy glue, moulding compounds and Cu-filled through-silicon-vias (TSVs) [2][3][4][5][6]. Thermal stress and warpage are frequently generated in the packaged chip during the thermal processing steps as a consequence of the CTE mismatch of these materials [7][8][9][10][11].…”
Section: Introductionmentioning
confidence: 99%
“…The fabrication process of a complete packaged IC is a tricky one, as it involves the use of different materials of distinct coefficients of thermal expansion (CTEs), e.g. die bond pad, die attach adhesive/epoxy glue, moulding compounds and Cu-filled through-silicon-vias (TSVs) [2][3][4][5][6]. Thermal stress and warpage are frequently generated in the packaged chip during the thermal processing steps as a consequence of the CTE mismatch of these materials [7][8][9][10][11].…”
Section: Introductionmentioning
confidence: 99%
“…An understanding of the visco-elastic-plastic characteristics of epoxy molding compounds is necessary to guarantee the reliability of IC performance. Thus far, many studies have been done on the thermo mechanical behavior of IC packages and epoxy molding compounds [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. However, mainly elastic or viscoelastic analysis has been carried out.…”
Section: Introductionmentioning
confidence: 99%
“…Suhir 52 evaluated the elastic stability of an epoxy cap in a flip-chip package design. Slattery et al 53 analyzed methods for predicting thermal stresses in plastic packages. Huang et al 54 modeled the possible occurrence of voiding in plastic packages.…”
Section: Thin Films Polymeric Materials and Plastic Packages Of Ic Dmentioning
confidence: 99%