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Double crosslinked chitosan–zeolite (CZ‐2) and noncrosslinked chitosan–zeolite (CZ‐0) composites were prepared and characterized by using Fourier transform infrared (FTIR) spectrometer, surface area analyzer, scanning electron microscope coupled with energy dispersive X‐ray (SEM‐EDX) spectrometer, thermogravimetric analyzer (TGA), X‐ray diffraction analyzer (XRD) and carbon, hydrogen, nitrogen (CHN) analyzer. After crosslinking, CZ‐2 showed a reduction in surface area and CHN content in comparison to chitosan, zeolite, and CZ‐0. Crosslinking resulted in improved stability of CZ‐2 in distilled water, acetic acid and NaOH as CZ‐2 recorded the lowest percentage of swelling. XRD diffractograms confirmed the formation of composites as there was a marked difference in the peak intensity at 2θ = 19.8°. © 2012 Wiley Periodicals, Inc. J Appl Polym Sci, 2012

The selection of appropriate characterisation methodologies is vital for analysing and comprehending the sources of defects and their influence on the properties of heteroepitaxially grown III-V layers. In this work we investigate the structural properties of GaAs layers grown by Metal-Organic Vapour Phase Epitaxy (MOVPE) on Ge substrates -(100) with 6⁰ offset towards <111> -under various growth conditions. Synchrotron X-ray topography (SXRT) is employed to investigate the nature of extended linear defects formed in GaAs epilayers. Other X-ray techniques, such as reciprocal space mapping (RSM) and triple axis ω-scans of (00l)-reflections (l = 2, 4, 6) are used to quantify the degree of relaxation and presence of antiphase domains (APDs) in the GaAs crystals. The surface roughness is found to be closely related to the size of APDs formed at the GaAs/Ge heterointerface, as confirmed by X-ray diffraction (XRD), as well as atomic force microscopy (AFM), and transmission electron microscopy (TEM).

Reliability issues as a consequence of thermal/mechanical stresses created during packaging processes have been the main obstacle towards the realisation of high volume 3D Integrated Circuit (IC) integration technology for future microelectronics. However, there is no compelling laboratory-based metrology that can non-destructively measure or image stress/strain or warpage inside packaged chips, System-on-Chip (SoC) or System-in-Package (SiP), which is identified as a requirement by the International Technology Roadmap for Semiconductors (ITRS). In the work presented here, a triple-axis Jordan Valley Bede D1 X-ray diffractometer is used to develop a novel lab-based technique called X-ray diffraction 3-dimensional surface modeling The feasibility of this technique is confirmed through the charactersation of die stress inside 2 encapsulated commercially available ultra-thin Quad Flat Non-lead (QFN) packages, as well as die stress in embedded QFN packages at various stages of the chip manufacturing process.

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