Metrology of white light interferometer for TSV processing

Timoney, Padraig; Ko, Yeong-Uk; Fisher, Daniel; Lu, Cheng Kuan; Ramnath, Yudesh; Vaid, Alok; Thangaraju, Sarasvathi; Smith, Daniel M.; Kamineni, Himani; Zhang, Dingyou; Kim, Wonwoo; Alapati, Ramakanth; Peak, Jonathan; Amin, Hemant; Edmunson, Holly; Race, Joe; Peterson, Brennan; Johnson, Tim

doi:10.1117/12.2047383

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“…A key component in 3D integration technology is the through‐silicon via (TSV), which electrically connects multiple strata of ICs vertically, enabling high‐performance, high functionality, compact heterogeneous systems with high data bandwidth and speed, and low power and low cost. Substantial research is being conducted on other aspects of TSVs, such as the design [4, 5], processing materials [6], metrology development [7, 8] and thermal–mechanical reliability [9]. The objective of this Letter is to investigate a new type of defect discovered during TSV process integration and manufacturing.…”

Section: Introductionmentioning

confidence: 99%

BMD impact on silicon fin defect at TSV bottom

et al. 2014

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A new type of through‐silicon via (TSV) defect, silicon fin defect, which was found after the TSV deep‐reactive‐ion‐etching process at the TSV bottom is reported. These defects are considered killer TSV defects that may cause process or mechanical failures and have to be eliminated. A scanning electron microscope automatic process inspection approach, which is non‐destructive and proven to be effective, has been established to image the fin defects at the bottom of the trench. A possible root cause of this defect is also explored. Both simulation and benchmarking test results indicate that bulk micro defects (BMDs) in the silicon substrate could serve as a micro‐mask during etching and result in silicon fin defects.

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