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In the semiconductor industry, chemical mechanical polishing (CMP) is utilized to planarize the surface of silicon wafers following the lithography and deposition steps, preparing the surface for subsequent layers of interconnects. Stringent local and global planarity tolerances are imposed by the feature size decreases and wafer size increases dictated by Moore’s law. The introduction of fragile, porous, oxide materials for their low dielectric constant also increases the fragility of the wafers being processed. An issue that has received significant attention in the literature is the relationship between the pressure distributed on the backside of the wafer and the resulting interfacial pressure between the wafer and the polishing pad. The Preston relationship for polishing of glass asserted proportionality between the applied pressure and the relative velocity to the resulting material removal rate. However, the pressure distribution between the pad and the wafer is not so well understood and therefore requires a detailed investigation. This paper presents results of a finite element model of CMP incorporating realistic boundary conditions for the wafer carrier and platen assemblies. The model predictions of interfacial contact pressure are validated by unique measurements of the contact pressure between the wafer and the pad using a static pressure measurement film and accompanying analysis software. The results demonstrate a close correlation between the model’s prediction and the measured values.