MEVBench: A mobile computer vision benchmarking suite

Clemons, Jason; Zhu, Haishan; Savarese, Silvio; Austin, Todd

doi:10.1109/iiswc.2011.6114206

Cited by 64 publications

(25 citation statements)

References 20 publications

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“…Memory System Characterizations: A wide range of papers have characterized memory system behavior for parallel applications [4,30], cloud/server applications [3,23], GPU applications [6,16], and mobile/embedded applications [8,11,12]. While these prior studies characterized the applications on a single type of platform, our work examines different implementations of the same applications for two different core types with the express goal of understanding the differences in architectural mapping.…”

Section: Related Workmentioning

confidence: 99%

A comparative analysis of microarchitecture effects on CPU and GPU memory system behavior

Hestness

Keckler

Wood

2014

2014 IEEE International Symposium on Workload Characterization (IISWC)

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Abstract-While heterogeneous CPU/GPU systems have been traditionally implemented on separate chips, each with their own private DRAM, heterogeneous processors are integrating these different core types on the same die with access to a common physical memory. Further, emerging heterogeneous CPU-GPU processors promise to offer tighter coupling between core types via a unified virtual address space and cache coherence. To adequately address the potential opportunities and pitfalls that may arise from this tighter coupling, it is important to have a deep understanding of application-and memory-level demands from both CPU and GPU cores. This paper presents a detailed comparison of memory access behavior for parallel applications executing on each core type in tightly-controlled heterogeneous CPU-GPU processor simulation. This characterization indicates that applications are typically designed with similar algorithmic structures for CPU and GPU cores, and each core type's memory access path has a similar locality filtering role. However, the different core and cache microarchitectures expose substantially different memory-level parallelism (MLP), which results in different instantaneous memory access rates and sensitivity to memory hierarchy architecture.

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Section: Related Workmentioning

confidence: 99%

A comparative analysis of microarchitecture effects on CPU and GPU memory system behavior

Hestness

Keckler

Wood

2014

2014 IEEE International Symposium on Workload Characterization (IISWC)

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“…We used the gem5 simulator in full-system mode to measure the performance impact of these designs [45]. For this second evaluation we assume a fault-free system and measure the impact of all necessary reliability mechanisms on the MEVBench benchmark suite [48]. Three main reasons led us to choose this set of benchmarks.…”

Section: A Experimental Setupmentioning

confidence: 99%

“…We use gem5 to evaluate 16 different fault-free CMP configurations executing the MEVBench benchmark suite [48]. In this analysis we consider computational epochs 20 million cycles long, a common choice for such systems.…”

Section: G Full System Performance Analysismentioning

confidence: 99%

Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation

Pellegrini

Bertacco

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-A modern digital system includes in a single chip many components: processing cores, large caches, memory controllers, and hardware accelerators. Looking forward, future semiconductor technologies will enable even higher device integration, overall increasing system performance while reducing energy consumption. Unfortunately, prominent experts agree that such technologies will be prone to both permanent and transient faults within their lifetime. With the goal of addressing this issue, we propose Cardio: a low-cost architecture for reliable chip multiprocessors. Our solution is based on a novel hardware/software co-design where silicon failures are detected in hardware and system reconfiguration is managed in software. Comparing Cardio with a state-of-the-art hardwarebased resiliency solution, Immunet, we found that our design can achieve a comparable fault response time while requiring a much lower area overhead. The proposed solution relies on a distributed resource manager to collect information about a CMP component's health, and leverages a synchronized distributed control mechanism to recover from permanent failures. Such architecture can operate as long as at least one general-purpose processor is still functional. Our experimental evaluation indicates that the overall performance impact of Cardio is as low as 4.5%, and its dynamic reconfiguration time upon fault detection is comprised between 20 and 50 thousand cycles.

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“…To account for the varied nature of data processing tasks, our proposed taxonomy helps to maintain consistency when extending this benchmark suite. For example, vision benchmark suites such as MEVBench [2] can be integrated into the occipital node of the suite.…”

Section: Introductionmentioning

confidence: 99%

CortexSuite: A synthetic brain benchmark suite

Thomas

Gohkale

Tanuwidjaja

et al. 2014

2014 IEEE International Symposium on Workload Characterization (IISWC)

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Abstract-These days, many traditional end-user applications are said to "run fast enough" on existing machines, so the search continues for novel applications that can leverage the new capabilities of our evolving hardware. Foremost of these potential applications are those that are clustered around information processing capabilities that humans have today but are lacking in computers. The fact that brains can perform these computations serves as an existence proof that these applications are realizable. At the same time, we often discover that the human nervous system, with its 80 billion neurons, on some metrics, is more powerful and energy-efficient than today's machines. Both of these aspects make this class of applications a desirable target for an architectural benchmark suite, because there is evidence that these applications are both useful and computationally challenging.This paper details CortexSuite, a Synthetic Brain Benchmark Suite, which seeks to capture this workload. We classify and identify benchmarks within CortexSuite by analogy to the human neural processing function. We use the major lobes of the cerebral cortex as a model for the organization and classification of data processing algorithms. To be clear, our goal is not to emulate the brain at the level of the neuron, but rather to collect together synthetic, man-made algorithms that have similar function and have met with success in the real world. We consulted six worldclass machine learning and computer vision researchers, who collectively hold 83,091 citations across their distinct subareas, asking them to identify newly emerging computationally-intensive algorithms or applications that are going to have a large impact over the next ten years. This is coupled with datasets that reflect the philosophy of practical use algorithms and are coded in "clean C" so as to make them accessible, analyzable, and usable for parallel and approximate compiler and architecture researchers alike.

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MEVBench: A mobile computer vision benchmarking suite

Cited by 64 publications

References 20 publications

A comparative analysis of microarchitecture effects on CPU and GPU memory system behavior

A comparative analysis of microarchitecture effects on CPU and GPU memory system behavior

Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation

CortexSuite: A synthetic brain benchmark suite

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