Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling

Moshovos, Andreas; Sohi, Gurindar S.

doi:10.1109/5.964438

Cited by 23 publications

(12 citation statements)

References 81 publications

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“…OOO processors may execute an instruction as long as this does not violate any program dependencies [1,3]. OOO can extract more ILP than a superscalar since in OOO, instructions executing in parallel do not have to be adjacent.…”

Section: Motivationmentioning

confidence: 99%

“…At the core of register renaming, is a register alias table (RAT) which maps architectural (RAT index) to physical (RAT values) registers [1,3,4,5]. Renaming an instruction for a three operand instruction set such as that of Nios II proceeds as follows: First, the current mapping of the two source registers are read from the RAT.…”

Section: Register Renamingmentioning

confidence: 99%

“…Superscalar processors use multiple datapaths to completely overlap the execution of multiple adjacent instructions. OOO processors allow instructions to execute in any order that does not violate program semantics and thus OOO can extract more parallelism than superscalar execution [1,3]. OOO execution can be used with a single or multiple datapaths and can extract even more parallelism via register renaming and speculative execution (Section 3).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming

Aasaraai

Moshovos

2009

2009 International Conference on Field Programmable Logic and Applications

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Section: Motivationmentioning

confidence: 99%

Section: Register Renamingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming

Aasaraai

Moshovos

2009

2009 International Conference on Field Programmable Logic and Applications

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“…In addition we need to deal with the decreased transistor size, as the leakage current increases we require more complicated process technology. In conclusion, this complicated situation where the number of transistors per unit area needs to increase, but the operating frequency must go down, will likely increase the number of cores required and decrease (not increase so quickly) the clock frequency [3,4].…”

Section: Introductionmentioning

confidence: 99%

Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications

Gepner¹,

Fraser²,

Kowalik³

2008

Lecture Notes in Computer Science

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Abstract. The second generation of Quad-Core Intel R Xeon R processors was launched on November 12th 2007. In this paper we take a look at what the new 45 nm based Quad-Core Intel Xeon Processor brings to high performance computing. We compare an Intel Xeon 5300 series based system with a server utilizing his successor the Intel Xeon 5400. We measure both CPU generations operating in dual socket platforms in typical HPC benchmark scenario using some common HPC benchmarks. The results presented clearly show that the new Intel Xeon processor 5400 family provides significant performance advantage on typical HPC workloads and would therefore be seen to be an appropriate choice for many of HPC installations.

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“…Here there were two major proposals: VLIW and dynamically-scheduled superscalar [20]. The former required a statically-created ILP program, whereas the latter achieved ILP by dynamically carrying out an instruction-level dataflow execution of a sequential program.…”

Section: Introductionmentioning

confidence: 99%

Dataflow execution of sequential imperative programs on multicore architectures

Gupta

Sohi

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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As multicore processors become the default, researchers are aggressively looking for program execution models that make it easier to use the available resources. Multithreaded programming models that rely on statically-parallel programs have gained prevalence. Most of the existing research is directed at adapting and enhancing such models, alleviating their drawbacks, and simplifying their usage. This paper takes a different approach and proposes a novel execution model to achieve parallel execution of statically-sequential programs. It dynamically parallelizes the execution of suitably-written sequential programs, in a dataflow fashion, on multiple processing cores. Significantly, the execution is race-free and determinate. Thus the model eases program development and yet exploits available parallelism. This paper describes the implementation of a software runtime library that implements the proposed execution model on existing commercial multicore machines. We present results from experiments running benchmark programs, using both the proposed technique as well as traditional parallel programming, on three different systems. We find that in addition to easing the development of the benchmarks, the approach is resource-efficient and achieves performance similar to the traditional approach, using stock compilers, operating systems and hardware, despite the overheads of an all-software implementation of the model.

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Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling

Cited by 23 publications

References 81 publications

Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming

Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming

Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications

Dataflow execution of sequential imperative programs on multicore architectures

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