Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

Abstract

This paper describes the architecture and implementation of the original gaming-oriented synergistic processor element (SPE) in both 90-nm and 65-nm silicon-on-insulator (SOI) technology and introduces a new SPE implementation targeted for the highperformance computing community. The Cell Broadband Enginee processor contains eight SPEs. The dual-issue, four-way singleinstruction multiple-data processor is designed to achieve high performance per area and power and is optimized to process streaming data, simulate physical phenomena, and render objects digitally. Most aspects of data movement and instruction flow are controlled by software to improve the performance of the memory system and the core performance density. The SPE was designed as an 11-FO4 (fan-out-of-4-inverter-delay) processor using 20.9 million transistors within 14.8 mm 2 using the IBM 90-nm SOI low-k process. CMOS (complementary metal-oxide semiconductor) static gates implement the majority of the logic. Dynamic circuits are used in critical areas and occupy 19% of the non-static random access memory (SRAM) area. Instruction set architecture, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power-efficient design. Correct operation has been observed at up to 5.6 GHz and 7.3 GHz, respectively, in 90-nm and 65-nm SOI technology.

Scaling and Its Implications for the Integration and Design of Thin Film and Processes

“…Strained SOI has become popular these days since it adds performance, meets demands of mobility, reduces gate leakage, and lowers power consumption [31]. Intel has used strained layers in the past to keep up performance due to scaling.…”

Extending the Cell SPE with Energy Efficient Branch Prediction

“…The Cell processor consists of one PPE (Power Processing Element) and eight SPEs (Synergistic Processing Elements) [4]. The PPE is a general purpose PowerPC that runs the operating system and controls the SPEs.…”

“…Flachs et al [4] present a voltage/frequency 'schmoo' that gives a power estimation for different frequencies and voltages. A 65nm SPE operates with Vdd= 0.9V [10].…”

Increasing memory miss tolerance for SIMD cores

“…The software controlled approach to diverge on miss outlined in Section 4.2 can be compared to the streaming approach of the Merrimac architecture [12] and the Cell chip's Synergistic Processing Units [13]. These architectures have explicit memory hierarchies and independent DMA engines, which can fetch lists of memory references into a large software controlled on-chip buffer asynchronously, without having to block execution.…”

“…If they miss, however, they do not block but are instead turned into implicit prefetches. By guaranteeing a fixed latency to completion, they have the benefit of being easy to schedule for the compiler in optimized loops, similar to accesses to scratchpad memories in other architectures [13].…”