Scaling and Its Implications for the Integration and Design of Thin Film and Processes

Seshan, K.

doi:10.1016/b978-1-4377-7873-1.00002-4

Cited by 19 publications

(18 citation statements)

References 41 publications

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“…For example, gate oxide thicknesses in semiconductors have been in the sub 10 nm range since the early 1990's. 53 When semiconductor technology reached the 22 nm node in 2011, the gate oxide thickness was down to 0.5-0.8 nm. 53 The target for diffusion barrier layer thickness at the 22 nm node is 3 nm.…”

Section: Application Of Leis To Semiconductors 39mentioning

confidence: 99%

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Low energy ion scattering (LEIS). A practical introduction to its theory, instrumentation, and applications

et al. 2016

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Section: Application Of Leis To Semiconductors 39mentioning

confidence: 99%

“…53 When semiconductor technology reached the 22 nm node in 2011, the gate oxide thickness was down to 0.5-0.8 nm. 53 The target for diffusion barrier layer thickness at the 22 nm node is 3 nm. 21 This downward trend in lm thicknesses will probably continue as technology advances to the 10 nm and 7 nm nodes.…”

Section: Application Of Leis To Semiconductors 39mentioning

confidence: 99%

Low energy ion scattering (LEIS). A practical introduction to its theory, instrumentation, and applications

et al. 2016

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“…It is assumed that at zero biasing sputtering of the deposited film does not take place since the ions have energy below the sputtering threshold. With an increase of substrate biasing, during the reverse sputtering Cu may undergo higher self-sputtering due to its higher sputtering yield than Ti [14]. The XRD patterns of the samples are presented in figure 3.…”

Section: Resultsmentioning

confidence: 99%

Characterization and antibacterial activity of co-sputtered Cu-doped TiO₂ coatings deposited on Ti6Al4V alloy

Nikolova,

Ilievska,

Handzhiyski

et al. 2024

J. Phys.: Conf. Ser.

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Copper has gained increased interest because of its important role in metabolism and antimicrobial activity. In this study, composite target material of Ti and Cu was used to deposit TiO2 coatings doped with copper on Ti6Al4V alloy. The aim was to examine the influence of the applied bias during the deposition of Cu-doped TiO2 coating by sputtering in a glow-discharge in a pure O2 atmosphere for a deposition time of 240 min. Different substrate values, selected from 0 to -150 V, were used in the process. The increase in bias voltage from -50 to - 150 V decreased the thickness of the oxide coatings and improved their adhesion to the substrate while increasing the Cu2O phase at the expense of a CuO phase decrease. Simultaneously, the increase in bias voltage decreased Cu content from about 32 wt% for the -50 V biased down to around 11 wt% for the -150 V biased specimens. The antimicrobial efficacy against E. coli estimated by direct contact experiments on the top of the uncoated (control) and coated Ti6Al4V alloy revealed about 94% inhibition for the -50V biased down to around 37% for the -150 V biased coatings as opposed to the control.

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“…Afterwards, we utilized a standard chemical mechanical polishing (CMP) process, stopping on the SiN hardmask, a process also typically used in CMOS fabrication for shallow trench isolation (STI). [36] Before removing the hardmask, we performed an oxide etch-back with diluted HF in an effort to lower the step height induced by the SiN mask removal. However, this approach typically results in a topography of a few nanometers locally at the edge of the waveguides.…”

Section: Fab-level Integration and Optimizationmentioning

confidence: 99%

Wafer‐Scale Integration of Single Layer Graphene Electro‐Absorption Modulators in a 300 mm CMOS Pilot Line

Brems

Yudistira

et al. 2023

Laser & Photonics Reviews

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Graphene-based devices have shown great promise for several applications. For graphene devices to be used in real-world systems, it is necessary to demonstrate competitive device performance, repeatability of results, reliability, and a path to large-scale manufacturing with high yield at low cost. Here, we select single-layer graphene electro-absorption modulators as test vehicle and establish their wafer-scale integration in a 300mm pilot CMOS foundry environment. A hardmask is used to shape graphene, while tungsten-based contacts are fabricated using the damascene approach to enable CMOS-compatible fabrication. By analyzing data from hundreds of devices per wafer, the impact of specific processing steps on the performance could be identified and optimized. After optimization, modulation depth of 50 ± 4 dB/mm is demonstrated on 400 devices measured using 6 V peak-to-peak voltage. The electrooptical bandwidth is up to 15.1 ± 1.8 GHz for 25µm-long devices. The results achieved are comparable to lab-based record-setting graphene devices of similar design and CVD graphene quality. By demonstrating the reproducibility of the results across hundreds of devices, this work resolves the bottleneck of graphene wafer-scale integration. Furthermore, CMOS-compatible processing enables co-integration of graphene-based devices with other photonics and electronics building blocks on the same chip, and for high-volume low-cost manufacturing.

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Scaling and Its Implications for the Integration and Design of Thin Film and Processes

Cited by 19 publications

References 41 publications

Low energy ion scattering (LEIS). A practical introduction to its theory, instrumentation, and applications

Low energy ion scattering (LEIS). A practical introduction to its theory, instrumentation, and applications

Characterization and antibacterial activity of co-sputtered Cu-doped TiO₂ coatings deposited on Ti6Al4V alloy

Wafer‐Scale Integration of Single Layer Graphene Electro‐Absorption Modulators in a 300 mm CMOS Pilot Line

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Scaling and Its Implications for the Integration and Design of Thin Film and Processes

Cited by 19 publications

References 41 publications

Low energy ion scattering (LEIS). A practical introduction to its theory, instrumentation, and applications

Low energy ion scattering (LEIS). A practical introduction to its theory, instrumentation, and applications

Characterization and antibacterial activity of co-sputtered Cu-doped TiO2 coatings deposited on Ti6Al4V alloy

Wafer‐Scale Integration of Single Layer Graphene Electro‐Absorption Modulators in a 300 mm CMOS Pilot Line

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Product

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Characterization and antibacterial activity of co-sputtered Cu-doped TiO₂ coatings deposited on Ti6Al4V alloy