Microarchitecture Optimizations for Exploiting Memory-Level Parallelism

Abstract

The performance of memory-bound commercial applications such as databases is limited by increasing memory latencies. In this paper, we show that exploiting memory-level parallelism (MLP) is an effective approach for improving the performance of these applications and that microarchitecture has a profound impact on achievable MLP. Using the epoch model of MLP, we reason how traditional microarchitecture features such as out-oforder issue and state-of-the-art microarchitecture techniques such as runahead execution affect MLP. Simulation results show that a moderately aggressive out-of-order issue processor improves MLP over an in-order issue processor by 12-30%, and that aggressive handling of loads, branches and serializing instructions is needed to attain the full benefits of large out-of-order instruction windows. The results also show that a processor's issue window and reorder buffer should be decoupled to exploit MLP more efficiently. In addition, we demonstrate that runahead execution is highly effective in enhancing MLP, potentially improving the MLP of the database workload by 82% and its overall performance by 60%. Finally, our limit study shows that there is considerable headroom in improving MLP and overall performance by implementing effective instruction prefetching, more accurate branch prediction and better value prediction in addition to runahead execution.

Cache Sharing Management for Performance Fairness in Chip Multiprocessors

“…Average MLP is needed to consider to estimate the average penalty of each cache miss. We derive the average MLP definition in [2] as the average number of useful outstanding off-chip requests when there is at least one outstanding off-chip requests, denoted by M LP avg . We have the following equation:…”

“…By taking MLP related cost of each cache miss into account, [12] modified the standard LRU replacement policy and higher performance guaranteed. [2] analyzed the microarchitecture impact on MLP and developed a detailed model to relating MLP to overall performance.…”

Last-Touch Correlated Data Streaming

“…The DBCP mechanism correlates data addresses to last-touch accesses, enabling DBCP to increase memory-level parallelism for dependent memory accesses. Modern out-of-order processors often stall, unable to overlap the latency of dependent L1D misses [5]. Correlating miss addresses with last-touch instruction traces enables the predictor to retrieve data-dependent blocks in parallel and enhances memory level parallelism for pointerdependent traversals (e.g., linked lists or trees).…”

Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution

“…Other work targeted at understanding, exploiting or optimizing runahead execution have been presented by Sorin et al [16] and Chou et al [9].…”