The electronics industry has consistently decreased the dimensions of structural components and they are now well into the nanoscale range. Naturally, a significant portion of the chip is composed of interconnects. Besides, the engineering problems associated with short wavelength lithography to achieve smaller components, the performance of increasing number of interconnections has become one of the biggest limiting factors in device performance.[1,2] The power loss, signal degradation, interconnection delays, and other performance limitations related to interconnects should be minimized. The importance of such a task can be seen from the perspective of power dissipation by computation elements. The energy dissipation density in electronic chips approaches that in nuclear reactors. [3,4]