Microfabrication Challenges for Silicon-based Large Area (>500 mm²) 3D-manifolded Embedded Microcooler Devices for High Heat Flux Removal

A Novel Hardmask-to-Substrate Pattern Transfer Method for Creating 3D, Multi-level, Hierarchical, High aspect-ratio Structures for Applications in Microfluidics and Cooling Technologies

“…2f). After the desired 3D profile has been etched in the SiO 2 layer through multiple lithography rounds, the wafer is placed in a deep Si etcher which achieves anisotropic profiles in Si via a time-multiplexed deep reactive ion (DRI) process often also termed Bosch etching process 54 . This etching step is a one-shot process which www.nature.com/scientificreports/ scales the 3D profile in the SiO 2 vertically by the Si:SiO 2 etch selectivity and transfers it to the Silicon underneath (Fig.…”

“…The average Si:SiO etch selectivity over a total 200 μm depth of etch was found to be around 270-290. This etching recipe was developed extensively by a previous work by Hazra et al who reported etch selectivity of 220-240, and etch rate of 8 μm/min 54 . The DSE recipe used by Hazra et al was also extremely aggressive in order to accommodate their extreme total etch height of 1000 μm, although this aggressive recipe leads to a reduced Si:SiO 2 selectivity.…”

“…The DSE recipe used by Hazra et al was also extremely aggressive in order to accommodate their extreme total etch height of 1000 μm, although this aggressive recipe leads to a reduced Si:SiO 2 selectivity. In our present study, the recipe was slightly modified (the silicon etching step, 'etchA' time was reduced to 3.1 s from 3.3 54 ) to increase selectivity and attain straighter, more anisotropic etch profile. The progression of etch for our characterization structures (perpendicularly placed straight channels arrays of different widths and spacings between 100 and 400 μm) were investigated.…”

“…Recently, an ingenious double-sided processing technique has been developed by several researchers [50][51][52][53] and using this technique they were able to create 2-level 3D manifold structures for high power electronics hot-spot (25-100 mm 2 footprint) cooling. Later, Hazra et al successfully demonstrated scalability of this process flow to create extremely large area (≥ 500 mm 2 ) high heat flux 3D manifolded micro-coolers 54 . However, this method is only suitable for creation of very specific 2-level structures which can be made via intersection of two designs etched from both sides of the wafer.…”

“…However, this method is only suitable for creation of very specific 2-level structures which can be made via intersection of two designs etched from both sides of the wafer. Furthermore, the yield of 3D structures made via conventional or doublesided micro-lithography techniques on rigid Si wafers, drop drastically to about 50% because of manual handling of fragile wafers which have already gone through a round of deep Si etch 54,55 . Thus, commercially, the creation of taller (≥ 10 μm) multi-level structures have traditionally been performed via chip stacking methods 50,56 .…”